Hardware-efficient implementation of dynamic element...

Details Hardware-efficient implementation of dynamic element... Hardware-efficient implementation of dynamic element...

2003-01-30

2004-09-21

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000

Reexamination Certificate

active

06795003

ABSTRACT:

BACKGROUND OF THE INVENTION
In high resolution digital-to-analog converters (DACs), performance metrics such as linearity and noise are nominally determined by the matching of parameters derived from physical quantities in the construction of the DACs on an integrated circuit (IC), such as width, length, thickness, doping, etc. As a general rule, for each additional bit of performance in the DAC, parameter matching needs to be twice as tight. This translates to an increase by a factor of four in the IC area required by the DAC. When the DAC resolution is in the 16-bit range, it is no longer practical/economical to use size alone to achieve the required matching.
Over-sampled (sigma-delta) DACs (also referred to as “converters”) alleviate the need for raw matching using single-bit conversion (so called 1-bit DACs in CD players). A single-bit DAC has only two points in a transfer function of the DAC, and thus is inherently linear. The function of a sigma-delta modulator with a one-bit quantizer is to approximate a high resolution low frequency signal with a high frequency two-level signal. The drawback here is this produces large amounts of out-of-band, for example, high frequency, noise.
One solution is to use more than two levels of quantization. For example, 17 levels may be used. However, now the linearity requirements apply to the fall resolution of the DAC. That is, for a 16-bit DAC, the transfer function of the DAC with these quantization levels must be collinear to 1 part in 2
16
, which is 1 part in 65,536. Such linearity is difficult to achieve with raw parameter matching of the single-bit DACs. Thus, there is need to achieve such linearity in a multi-level DAC using an alternative to raw parameter matching.
Multi-bit DACs have the advantage of significantly increasing the precision limit of the single-bit converter. The major drawback of the multi-bit DAC is the non-linearity presented by the imperfect analog circuit mismatches. Specifically, the non-linearity stems from the mismatching between the unit DAC elements, and causes significant performance degradation. Since the multi-bit DAC is outside the &Dgr;-&Sgr; modulator, its error cannot be eliminated by the noise-shaping loop of the &Dgr;-&Sgr; modulator, while the quantization noise inside the &Dgr;-&Sgr; modulator can be noise-shaped by the &Dgr;-&Sgr; modulator feedback loop.
There has been a lot of literatures discussing about ways to noise-shape the mismatching error. See,. e.g., I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters”,
IEEE Trans. on Circuits and Systems
-
II: Analog and Digital Signal Processing
, pp. 808-817, vol. 44, no. 10, October 1997; J. Grilo et al., “A 12-mW ADC Delta-Sigma Modulator with 80dB of Dynamic Range Integrated in a Single-Chip Bluetooth Transceiver”,
IEEE Journal of Solid-State Circuits
, pp. 271-278, vol. 37, March 2002; J. Welz, I. Galton, and E. Fogleman, “Simplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Converters”,
IEEE Trans. on Circuits and Systems
-
II: Analog and Digital Signal Processing
, pp, 1014-1027, vol. 48, no. 11, November 2001; R. Adams et al., “A 113-dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling”,
IEEE Journal of Solid
-
State Circuits
, pp. 1871-1878, vol. 33, no. 12, December 1998; T. Kwan et al., “A Stereo Multibit &Sgr;&Dgr; DAC with Asynchronous Master-Clock Interface”,
IEEE Journal of Solid
-
State Circuits
, pp. 1881-1887, vol. 31, no. 12, December 1996; A. Yasuda et al., “A Third-Order &Dgr;-&Sgr; Modulator Using Second-Order Noise-Shaping Dynamic Element Matching”,
IEEE Journal of Solid
-
State Circuits
, pp. 1879-1886, vol. 33, no. 12, December 1998; R. Radke et al., “A Spurious-Free Delta-Sigma DAC Using Rotated Data Weighted Averaging”,
IEEE Custom Integrated Circuits Conference,
1999, pp.125-128; R. Radke and T. S. Fiez, “Improved &Sgr;&Dgr; DAC linearity using data weighted averaging”,
IEEE International Symposium
, vol.1, pp. 13-16, 1995; R. Radke et al., “A 14-bit Current-Mode &Sgr;&Dgr; DAC Based Upon Rotated Data Weighted Averaging”,
IEEE Journal of Solid
-
State Circuits
, vol. 35, no. 8, August 2000. The tree-structure (see I. Galton; J. Grilo et al.; and J. Welz et al., cited above) is one of the best noise-shaping structure, in which the input thermometer code is split into two numbers, which then into four numbers, and so on. The swapping cells is controlled by the Parity Detector outputs, and internally performing arithmetic operations to switch the inputs. The tree-structure results in controlled spectral shaping of the DAC mismatch errors. However, some residual non-linearity due to the DEM remains.
SUMMARY OF THE INVENTION
The present invention is directed to a hardware-efficient implementation of dynamic element matching in sigma-delta DAC's, that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided a data shuffler apparatus for shuffling input bits including a plurality of bit shufflers each inputting corresponding two bits x
0
and x
1
of the input bits and outputting a vector {x
0
′, x
1
} such that
Vector
Current State
Input Bits
Next State
{x
0
′, x
1
′}
S
0
(0)
x
0
= x
1
S
0
(0)
{x
0
, x
1
}
S
0
(0)
x
0
≠ x
1
S
1
(1)
{x
1
, x
0
}
S
1
(1)
x
0
= x
1
S
1
(1)
{x
0
, x
1
}
S
1
(1)
x
0
≠ x
1
S
0
(0)
{x
0
, x
1
}
At least two 4-bit vector shufflers input the vectors {x
0
′, x
1
′} and output 4-bit vectors each corresponding to a combination of two vectors {x
0
′, x
1
′}, such that the 4-bit vector shufflers operate on the vectors {x
0
′, x
1
′} in the same manner as the bit shufflers operate on the bits x
0
and x
1
. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
In another aspect there is provided a data shuffler apparatus for shuffling input bits including a plurality of bit shufflers each inputting corresponding two bits x
0
and x
1
of the input bits and outputting a vector {x
0
′, x
1
′} such that a number of 1's at bit x
0
′ over time is within ±1 of a number of 1's at bit x
1
′. At least two 4-bit vector shufflers input the vectors {x
0
, x
1
}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x
0
′, x
1
′} produced by the bit shufflers, such that the 4bit vector shufflers operate on the vectors {x
0
′, x
1
′} in the same manner as the bit shufflers operate on the bits x
0
and x
1
. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
In another aspect there is provided a digital to analog converter including an interpolation filter receiving an N-bit digital input. A delta-sigma modulator receiving an output of the interpolation filter. A dynamic element matching encoder receives N bits from the delta-sigma modulator, and outputs an analog signal corresponding the digital input. The dynamic element matching encoder includes a plurality of bit shufflers each inputting two bits x
0
and x
1
of the N bits, and outputting a vector {x
0
′, x
1
′} such that a number of 1's at bit x
0
′ over time is within ±1 of a number of 1's at bit x
1
′. A plurality of vector shufflers arranged both in parallel and in successive levels input the vectors {x
0
, x
1
′} and output vectors each corresponding to a combination of vectors produced by a previous set of shufflers. The vector shufflers operate on their respective input vectors in the same manner as the bit shufflers operate on the bits x
0
and x
1
. The current state of the bit shufflers is updated based on a next state of the last level of the vector shufflers.
In another aspect there is provided a method of shuffling a plurality of input

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