Hardware control structure and method for off-chip monitoring en

Details Hardware control structure and method for off-chip monitoring en Hardware control structure and method for off-chip monitoring en

1991-06-14

1997-06-03

Swann, Tod R.

G06F 1208

Patent

active

056363630

ABSTRACT:
A structure and a method for directing execution of instructions are provided in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, when a signal is received on a second mode pin indicating that an instruction is to be provided on the memory bus is desired, a cache miss is generated at the next instruction fetch. Thus, the processor is forced to fetch the next instruction from main memory. The instruction is then provided on the memory bus as though it is fetched from the main memory in response to the read cycle resulting from the cache miss.

REFERENCES:
patent: 4190885 (1980-02-01), Joyce et al.
patent: 4686621 (1987-08-01), Keeley et al.
patent: 4991090 (1991-02-01), Emma et al.

Affiliated with

Also associated with

Rating

Hardware control structure and method for off-chip monitoring en does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hardware control structure and method for off-chip monitoring en, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware control structure and method for off-chip monitoring en will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-399289