Patent
1997-03-31
1999-03-09
Harrell, Robert B.
G06F 900
Patent
active
058812580
ABSTRACT:
A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently executes old software code by providing the processor with a compatibility circuit which receives old software code instructions from a secondary memory, groups these instructions according the new instruction set architecture and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.
REFERENCES:
patent: 5568646 (1996-10-01), Jaggar
Siamak Arya, "A Mechanism For Hardware Compatibility For A New Architecture", Advanced Development Group, SPARC Technology Business, Sun Microsystems, Inc., pp. 1-5.
Harrell Robert B.
Sun Microsystems Inc.
Terrile Stephen A.
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