Hardware-based multi-threading for packet processing

Details Hardware-based multi-threading for packet processing Hardware-based multi-threading for packet processing

2004-03-31

2010-02-23

Harper, Kevin C (Department: 2416)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C718S100000, C718S106000, C710S100000

Reexamination Certificate

active

07668165

ABSTRACT:
Methods and apparatus for processing transmission control protocol (TCP) packets using hardware-based multi-threading techniques. Inbound and outbound TCP packet are processed using a multi-threaded TCP offload engine (TOE). The TOE includes an execution core comprising a processing engine, a scheduler, an on-chip cache, a host memory interface, a host interface, and a network interface controller (NIC) interface. In one embodiment, the TOE is embodied as a memory controller hub (MCH) component of a platform chipset. The TOE may further include an integrated direct memory access (DMA) controller, or the DMA controller may be embodied as separate circuitry on the MCH. In one embodiment, inbound packets are queued in an input buffer, the headers are provided to the scheduler, and the scheduler arbitrates thread execution on the processing engine. Concurrently, DMA payload data transfers are queued and asynchronously performed in a manner that hides memory latencies. In one embodiment, the technique can process typical-size TCP packets at 10 Gbps or greater line speeds.

REFERENCES:
patent: 7181742 (2007-02-01), Hooper
patent: 2004/0199808 (2004-10-01), Freimuth et al.
patent: 2005/0027793 (2005-02-01), Hass
patent: 2005/0122986 (2005-06-01), Starr et al.

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