Hardware-based encryption/decryption employing dual ported...

Cryptography – Communication system using cryptography – Data stream/substitution enciphering

Reexamination Certificate

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C711S200000

Reexamination Certificate

active

06980649

ABSTRACT:
A system for the encryption and decryption of data employing dual ported RAM to accelerate data processing operations during the computation of the encryption and decryption algorithm. The system includes logic to track data changes in the dual ported memory for fast table initialization; a means to accelerate operations by performing read/write operations in different iterations of the algorithm to separate ports on the dual ported RAM in the same clock cycle; and a means to resolve data manipulation conflicts between out of order read/write operations so that the system correctly computes the desired algorithm.

REFERENCES:
patent: 6549622 (2003-04-01), Matthews, Jr.
patent: 6570989 (2003-05-01), Ohmori et al.
P. Hämäläinen, M. Hännikäinen, T. Hämäläinen, and J. Saarinen, “Hardware Implementation of the Improved WEP and RC4 Encryption Algorithms for Wireless Terminals”, 10th European Signal Processing Conference, EUSIPCO2000, Tampere, Finland, Sep. 5-8, 2000.
Greg Rose and Philip Hawkes, “Turing: A Fast Stream Cipher”, Qualcomm, Nov. 30, 2000.
M. Galanis, P. Kitsos, G. Kostopoulos, O. Koufopavlou, C. Goutis, “Comparison of the Performance of the Stream Ciphers for Wireless Communications”, VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras,Greece. 2004.
P. Kitsos, G. Kostopoulos, N. Sklavos, and O. Koufopavlou, “Hardware Implementation of the RC4 Stream Cipher”, Proceedings of the 46th IEEE Midwest Symposium on Circuits & Systems (MWSCAS), Cairo, Egypt, Dec. 27-30, 2003.

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