Hardware-based CABAC decoder with parallel binary arithmetic...

Details Hardware-based CABAC decoder with parallel binary arithmetic... Hardware-based CABAC decoder with parallel binary arithmetic...

2007-08-28

2007-08-28

Nguyen, Linh (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from code based on probability

C341S065000, C341S067000

Reexamination Certificate

active

11474897

ABSTRACT:
A binary arithmetic decoding apparatus includes first, second and third pairs of look-up tables and first, second and third multiplexers. The first multiplexer selects between the respective outputs of the two look-up tables of the first pair of look-up tables. The second multiplexer selects between the respective outputs of a first look-up table of the second pair of look-up tables and of a first look-up table of the third pair of look-up tables. The third multiplexer selects between the respective outputs of a second look-up table of the second pair of look-up tables and of a second look-up table of the third pair of look-up tables. The three multiplexers are controlled in common.

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Detlev Marpe et al., “Context-Based Adaptive Binary Arithmetic Coding in the H.264/AVC Video Compression Standard”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, No. 7, Jul. 2003. ISSN: 1051-8215, pp. 620-636.

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