Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-05-30
2006-05-30
Rodriguez, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S014000, C714S028000, C714S033000, C716S030000
Reexamination Certificate
active
07054802
ABSTRACT:
A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.
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Orrick Herrington & Sutcliffe LLP
Quickturn Design Systems Inc.
Rodriguez Paul L.
Sharon Ayal
LandOfFree
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