Hardware arrangement for storing error information in pipelined

Details Hardware arrangement for storing error information in pipelined Hardware arrangement for storing error information in pipelined

1989-07-26

1992-05-05

Atkinson, Charles E.

Excavating

371 491, 371 511, G06F 1110

Patent

active

051114585

ABSTRACT:
In order to simplify a hardware arrangement for obtaining error information in a pipelined data processing system which includes serially coupled stages, two separate (first and second) error signal storage means are provided. The first error signal storage means has a plurality of one-bit (for example) memory cells which are respectively assigned to the pipeline stages. The first error signal storage means defines one pipeline stage in which an error is initially detected. The second error signal storage means responds to an error detection signal and receives error analyzing information from the last stage of the pipeline.

REFERENCES:
patent: 4414669 (1983-11-01), Heckelman et al.
patent: 4660198 (1987-04-01), Lyon
patent: 4745605 (1988-05-01), Goldman et al.

Affiliated with

Also associated with

Rating

Hardware arrangement for storing error information in pipelined does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hardware arrangement for storing error information in pipelined , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware arrangement for storing error information in pipelined will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1418722