Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Event-driven
Reexamination Certificate
2001-08-20
2004-06-15
Frejd, Russell (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Event-driven
C703S019000, C703S020000, C703S022000, C717S127000
Reexamination Certificate
active
06751583
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer software and hardware simulators, and more specifically, to a system and method to simulate an electronic system that includes one or more target processors executing software and interacting with hardware.
BACKGROUND
Computer simulation of digital hardware systems has become a common technique to reduce the cost and time required for the design of such hardware systems. Simulating digital hardware allows a designer to predict the functioning and performance of the hardware prior to fabricating the hardware.
More and more digital systems incorporate a processor, including a microprocessor, a digital signal processor, or other special purpose computer processor. There has been increased effort to develop a simulation system that includes simulating the hardware and simulating the running of software on one or more processors that are included in the digital system. Having such a simulation system allows a designer to test the operation of software on the processor(s) before a physical processor is available. Thus, for example, a designer may be able to start designing a system incorporating a new microprocessor before the manufacturer actually releases physical samples of the microprocessor. In addition, a system designer designing an integrated circuit or a system on a printed circuit board that includes a processor can, for example, use the simulation system to test the integrated circuit or printed circuit board implementation, including operation of software on the processor part, and any testing interactions between the processor and the other digital circuit elements of the integrated circuit or board, before the integrated circuit or board is fabricated. This clearly can save time and money.
Nomenclature
A simulation system for simulating both the digital hardware that includes one or more target processors and the running of software on the processor(s) is called a co-simulation design system, a co-simulation system, or simply a design system herein, and the environment for operating such a co-simulation system is called a design environment. The processor is called a target processor and the computer system on which the environment operates is called the host computer system or simply the host. The host computer system includes one or more host processors. The hardware other than the target processor is called digital circuitry. The computer software program that is designed by a user to operate on the target processor is called the user program or the target code.
The target processor typically includes memory and one or more caches, for example a data cache (or D-cache) and an instruction cache (or I-cache). The target processor typically may also include a memory management unit (MMU) that converts virtual addresses into physical memory addresses and possibly physical I/O device addresses. The MMU may include a translation lookaside buffer (TLB) to improve address translation performance. A TLB is a hardware element that acts as a cache of recent translations and stores virtual memory page to physical memory page translations. Given a memory address (an instruction to fetch, or data to load or store), the target processor first looks in the TLB to determine if the mapping of virtual page to physical page is already known. If so (a “TLB Hit”), the translation can be done quickly. But if the mapping is not in the TLB (a “TLB Miss”), the correct translation needs to be determined.
The target processor may be a separate microprocessor with the digital circuitry being external to the microprocessor (e.g., on a printed circuit board or elsewhere in the system), or may be a processor embedded in an application specific integrated circuit (ASIC) or a custom integrated circuit (IC) such as a very large scale integrated (VLSI) device, with the digital circuitry including some components that are part of the ASIC or IC, and other components that are external to the ASIC or IC.
The host processor also includes memory, and the host memory is referred to as “host memory” herein. The physical address of the host memory is referred to as the “host address” herein. When the word “address” is used without specifying the host, then it refers to the target address.
Desirable Aspects for a Co-Simulation Design System
A design environment capable of co-simulation requires the capability of accurately simulating the digital circuitry, including timing, and the capability of accurately simulating the running of the user program (i.e., the target code) on the target processor, including the accurate timing of operation of the user program and of any software/hardware interaction. The first requirement is available today in a range of simulation environments using hardware description languages (HDLs) such as Verilog and VHDL. It also is available as a set of constructed libraries and classes that allows the modeling of hardware in a higher-level language such as ‘C’ or ‘C++.’ The second requirement pertains to a processor simulator using an executable processor model that both accurately simulates the execution of a user program on the target processor, and can interact with the digital circuitry simulation environment. Such a processor simulator should provide timing information, particularly at times of software/hardware interaction, i.e., at the software/hardware interface. A processor model that includes such accurate timing information is called a “quantifiable” model herein.
One known way of providing such processor simulation is to simulate the actual hardware design of the processor, for example by specifying a processor model in a hardware description language (HDL). The main but great disadvantage of so simulating the operation of the processor is the slow execution speed, typically in the range of 0.1-100 instructions per second.
Another known way of accurately simulating the execution of software on a processor for inclusion in a co-simulation environment is an instruction set simulator (ISS), wherein both the function and the sequencing of the microprocessor is mimicked in software. An instruction set simulator still executes relatively slowly, compared for example to how fast a program would be executing on the target processor. An ISS executes in the range of 1,000 to 50,000 instructions per second depending on the level of timing and operational detail provided by the model.
Real systems execute 50-1000 million instructions per second or more, so that the ISS or full hardware simulation techniques have a disparity of a factor between about 10,000 to 200,000 in performance; 3 to 60 hours of simulation may be needed to model 1 second of real-time target processor performance.
One solution to the slow speed of simulating a processor is to use a hardware processor model. This device includes a physical microprocessor and some circuitry for interfacing and interacting with the design environment simulating the digital circuitry. The memory for the target processor is simulated as part of the digital circuitry. Such an approach is fairly expensive. Another limitation is due to having two definitions of time operating on the same simulation system: simulation time of a hardware simulator, and processor time, which is real time for the hardware processor. Correlating these is difficult.
Another solution is to use an emulator as the target processor model. An emulator, like a hardware processor model, is a hardware device, typically the target processor, and usually includes some memory. The emulator is designed to emulate the operation of the microprocessor. Such a processor emulator when it includes memory can execute the user program directly, but again is expensive and may require the development of external circuitry to interact with the hardware simulator simulating the digital circuitry. U.S. Pat. No. 5,838,948 describes an environment that uses an emulator for speeding up the running of a user program in the design environment.
While sometimes it is desired to run a simulation with great precision at
Clarke Neville A.
Torossian James R.
Frejd Russell
Inventek
Rosenfeld Dov
VaST Systems Technology Corporation
LandOfFree
Hardware and software co-simulation including simulating a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hardware and software co-simulation including simulating a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware and software co-simulation including simulating a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3313559