Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2005-09-28
2008-10-28
Rodriguez, Paul L (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C712S011000, C712S024000, C326S037000
Reexamination Certificate
active
07444276
ABSTRACT:
A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.
REFERENCES:
patent: 4736663 (1988-04-01), Wawrzynek et al.
patent: 5093920 (1992-03-01), Agrawal et al.
patent: 5384275 (1995-01-01), Sakashita
patent: 5448496 (1995-09-01), Butts et al.
patent: 5572710 (1996-11-01), Asano et al.
patent: 5655133 (1997-08-01), Dupree et al.
patent: 5663900 (1997-09-01), Bhandari et al.
patent: 5734581 (1998-03-01), Butts et al.
patent: 5737631 (1998-04-01), Trimberger
patent: 5958048 (1999-09-01), Babaian et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6058492 (2000-05-01), Sample et al.
patent: 6097886 (2000-08-01), Dave et al.
patent: 6298366 (2001-10-01), Gatherer et al.
patent: 6377912 (2002-04-01), Sample et al.
patent: 6385757 (2002-05-01), Gupta et al.
patent: 6523055 (2003-02-01), Yu et al.
patent: 6530014 (2003-03-01), Alidina et al.
patent: 6553479 (2003-04-01), Mirsky et al.
patent: 6604065 (2003-08-01), Blomgren et al.
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 6678646 (2004-01-01), McConnell et al.
patent: 6684318 (2004-01-01), DeHon et al.
patent: 6745317 (2004-06-01), Mirsky et al.
patent: 6766445 (2004-07-01), Schlansker et al.
patent: 7080365 (2006-07-01), Broughton et al.
patent: 7107432 (2006-09-01), De Vries et al.
patent: 2001/0020224 (2001-09-01), Tomita
patent: 2001/0025238 (2001-09-01), Kitajima et al.
patent: 2003/0105617 (2003-06-01), Cadambi et al.
patent: 2004/0054518 (2004-03-01), Altman et al.
patent: 2005/0256696 (2005-11-01), Gooding et al.
patent: 2006/0089829 (2006-04-01), Gooding et al.
patent: 64-26969 (1989-01-01), None
patent: 2001-222564 (2001-08-01), None
patent: 2001-249824 (2001-09-01), None
Haug et al, “Behavioral Emulation of Synthesized RT-level Descriptions Using VLIW Architectures”, Proceedings of the 1998 Ninth International Workshop on Rapid System Prototyping, Jun. 3-5, 1998.
Lewis et al, “A Programmable Hardware Accelerator for Compiled Electrical Simulation”, 25th ACM/IEEE Design Automation Conference, 1988.
Abke, J. et al., “A New Placement Method for Direct Mappings into LUT-Based FPGAs. In International Conference on Field Programmable Logic and Applications (FPL 2001),” Aug. 2001, pp. 27-36.
Abramovici, M. et al., “A Logic Simulation Machine,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sytems, Apr. 1983, pp. 82-94, vol. CAD-2, No. 2.
“ADC-RC1000 Virtex Reconfigurable Computing PCI Card” Alpha Data Parallel System, Online! May 20, 2002, pp. 1-3 XP002275523.
Babb, J. et al., “Logic Emulation with Virtual Wires,” In IEEE Transactions on CAD of Integrated Circuits and Systems, Jun. 1997.
Babb, J. et al., “Virtual Wires: Overcoming Pin Limitations in FPGA-Based Logic Emulators,” In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1993.
Cadambi, S. et al., “Efficient Place and Route for Pipeline Reconfigurable Architecture,” IEEE, 2000, pp. 423-429.
Cadambi et al., “A Fast, Inexpensive and Scalable Hardware Acceleration Technique for Functional Simulation” Proceedings of Design Automation Conference 2002, Jun. 10, 2002, pp. 570-575.
“The Challenge of Design Complexity: The Power of Simulation Acceleration and Emulation” [online] [Retrieved on Jan. 15, 2004] Retrieved from the Internet<URL:http://www.quickturn.com/products/palladium.htm.
Cong, J. et al., “FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Design,” In IEEE Transactions on CAD, Jan. 1994, pp. 1-12.
Corno, F. et al., “RT-level ITC99 Benchmarks and First ATPG Results” IEEE Design and Test of Computers, Jul. 2000, pp. 44-53.
Goldstein, S.C. et al., “Piperench: A Coprocessor for Streaming Multimedia Acceleration,” The 26th Annual International Symposium on Computer Architecture, May 1999, pp. 28-39.
Hauck, S. et al., “Logic Partition Orderings for Multi-FPGA Systems,” ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb. 1995, pp. 32-38.
Hauck, S: “The Roles of FPGAs in Reprogrammable Systems” Proceedings of the IEEE, Apr. 1998, pp. 615-638, vol. 86, No. 4.
Lo, W et al., “Hardware Emulation Board Bases on FPGA's and Programmable Interconnections,” Proceedings of the Fifth International Workshop on Rapid System Prototyping, Jun. 21, 1994, pp. 126-130.
Mulpuri, C. et al., Runtime and Quality Tradeoffs in FPGA Placement and Routing, International Symposium on Field Programmable Gate Arrays, Feb. 2001, pp. 29-36.
Partial European Search Report, EP 03251837, May 5, 2004, 3 pages.
Sangiovanni-Vincentelli, A. et al., “Synthesis Methods for Field-Programmable Gate Arrays,” Proceedings of the IEEE, Jul. 1993, pp. 1057-1083, vol. 81, No. 7.
Semiconductor Industry Association. International technology roadmap for semiconductors, 1999, [online] [Retrieved on Jan. 15, 2004] Retrieved from the Internet<URL:http://public.itrs.net>.
Shriver, E., et al., “Ravel: Assigned-Delay Compiled-Code Logic Simulation,” International Conference on Computer-Aided Design (ICCAD), 1992, pp. 364-368.
“Sometimes, size does matter”, 2001, [online] [Retrieved on Jan. 15, 2004] Retrieved from the Internet<URL:http://www.quickturn.com/products/CoBALTUltra.htm>.
Spillinger, I. et al., “Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine,” IEEE Transactions on Computer-Aided Design, Jul. 1986, pp. 396-404, vol. CAD-5, No. 3.
Trimberger, S. et al., “Scheduling Designs into a Time-Multiplexed FPGA,” Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, Feb. 1998.
Trimberger, S. et al., “A Time-Multiplexed FPGA,” IEEE Symposium on FPGAs for Custom Computing Machines (FCCM) 1997, Feb. 1997.
Weinhardt et al.: “Memory access optimization for reconfigurable systems” IEEE Proceedings Computers and Digital Techniques, May 2001, pp. 105-112, p. 102, column 1-p. 106, column 1, vol. 148, No. 3.
Westgate, K. et al. “Reducing Logic Verification Time with Cycle Simulation,” 2000, http://www.quickturn.com/tech/cbs.htm.
“What is Cycle-Based Simulation,” [online] [Retrieved on Jan. 15, 2004] Retrieved from the Internet<URL:http://www.quickturn.com/products/speedsim.htm>.
Cadambi, S. et al., “A Fast, Inexpensive and Scalable Hardware Acceleration Technique for Functional Simulation,” Proceedings of Design Automation Conference, Jun. 10, 2002, pp. 570-575.
Mano et al., Logic and Computer Design Fundamentals, 2001, Second Edition, Prentice Hall, pp. 27-33.
Buchholz, T. et al. “Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures,” Proceedings of the 1998 Ninth International Workshop on Rapid System Prototyping, Jun. 3-5, 1998, 6 pages.
Budiu, M. et al., “Fast Compilation for Pipelined Reconfigurable Fabrics,” Carnegie Mellon University, ACM, 1999, pp. 195-205.
Cadambi, S. et al., “Managing Pipeline-Reconfigurable FPGAs,” Carnegie Mell
Verheyen Henry T.
Watt William
Fenwick & West LLP
Jacob Mary C
Liga Systems, Inc.
Rodriguez Paul L
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