Hard-wired circuit for handling screen windows

Details Hard-wired circuit for handling screen windows Hard-wired circuit for handling screen windows

1985-02-19

1987-06-02

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340744, 340724, 340747, G09G 114

Patent

active

046707522

ABSTRACT:
The window handler circuit is inserted between an image memory (7) having as many pages as there are possible windows and a screen controller capable of reading from any of the pages of the image memory. The handler comprises two auxiliary memories (3, 4) each of which stores bit maps in which a logic one bit indicates that the corresponding window includes an image element in the same line or the same column as the case may be as the screen position currently being scanned. A battery (5) of AND gates receives the line and column bit maps associated with the current screen position and generates a third bit map in which each logic one bit indicates that the corresponding window includes an image element at the current screen position. A priority encoder (6) then selects the visible or "uppermost" window from the said third bit map by generating the number (N) of the page to be read in the image memory (7). Relatively little memory is dedicated to determining the uppermost window at any screen position, since a two-dimensional array (the window bit map for each screen position) is generated from two one-dimensional arrays.

REFERENCES:
patent: 4197590 (1980-04-01), Sukonick et al.
patent: 4295135 (1981-10-01), Sukonick
patent: 4533910 (1985-08-01), Sukonick et al.
patent: 4542376 (1985-09-01), Bass et al.
patent: 4554538 (1985-11-01), Bieneman

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