Hard mask process to control etch profiles in a gate stack

Details Hard mask process to control etch profiles in a gate stack Hard mask process to control etch profiles in a gate stack

2000-04-25

2002-11-05

Goudreau, George (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000, C438S717000, C438S734000, C438S740000, C134S001200, C134S001300

Reexamination Certificate

active

06475922

ABSTRACT:

FIELD OF INVENTION
The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to process that increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack by use of a hard mask.
BACKGROUND OF INVENTION
One important stage in the manufacture of a semiconductor device involves photolithography and etching. In photolithography, The pattern is defined on the wafer substrate. The wafer is then etched. Depending upon the production process, the etching may either be a wet etch in which liquid chemicals are used to remove wafer material or a dry etch in which wafer material is subjected to a radio frequency (RF) induced plasma.
In many modem sub-micron processes, the gate electrode of a transistor is comprised of a composite of layers of materials “stacked” on top of one another, hence the name, “gate stack.” A commonly used gate stack is amorphous silicon (&agr;-Si) or poly silicon (poly-Si) on top of a thin gate oxide. The &agr;-Si or poly-Si is typically doped (by ion implantation) with N-type carriers for NMOS or with P-type carriers for PMOS to minimize poly depletion for NMOS devices and to improve PMOS device characteristics. After the implantation, an organic or in-organic anti-reflection coating (ARC) is deposited on top of the gate stack to reduce reflection for better critical dimension (CD) control on the gate. As IC dimensions are reduced in size, thinner gate oxide is required to maintain an acceptable level of gate capacitance.
Different doping types, doses, and activation levels of the &agr;-Si or poly-Si have significant effects on the &agr;-Si or poly-Si etch rate as well as the etch profile of the gate stack. N-doped &agr;-Si or poly-Si usually etches faster than P-doped &agr;-Si or poly-Si in a plasma etch process. Under the N-type material, thin gate oxide may be exposed to the plasma and removed when etching the remaining P-type material after the N-type material has been cleared. A localized breakthrough, “microtrenching,” of the thin gate oxidation in the bottom of the &agr;-Si or poly-Si etch features can result. Micro-trenches are small trenches formed in the bottom of the &agr;-Si features mostly adjacent to the sidewall, and the subsequent rapid etching of the underlying silicon.
With a relatively thin gate oxide, microtrenching is problematic, especially in N-doped areas. In a plasma etch process, a gate etch profile is also very sensitive to the doping of &agr;-Si or poly-Si. In addition, the doping characteristics between N-doped and P-doped &agr;-Si or poly-Si may be different especially for dense &agr;-Si or poly-Si lines. Consequently, there may also be unacceptable critical dimension (CD) variation among gate stacks in dense and sparse areas. Such CD variation in the gate significantly affects the performance of the manufactured devices.
Accordingly, a need exists for a gate etch process that is substantially free of micro-trenching and achieves consistent etch profiles in N/P-type doped gate stacks, as well as good critical dimension control as the process technology approaches fractional microns.
SUMMARY OF INVENTION
The present invention is exemplified in a number of implementations, one of which is summarized below. During the forming of gate stack structures of a transistor, the invention minimizes microtrenching of the thin gate oxide adjacent to the silicon gate structures. Additionally, the invention provides for gate etch profiles which are nearly vertical and consistent across the wafer. In accordance with a first embodiment of the invention, there is a method for etching a gate stack. The gate stack has a hard mask layer formed on a doped silicon layer on an insulating layer, the hard mask layer has a pattern defined thereon; and the pattern has masked areas and unmasked areas on a substrate. The method comprises first etching through unmasked areas of the hard mask layer and a predetermined amount of the doped silicon layer, with a first etch. The masked areas of the pattern are removed. With a second etch, etching of the doped silicon layer is resumed until the insulating layer is exposed. The remaining doped silicon layer is over-etched with a third etch until silicon residues are cleared. An additional feature of this embodiment is that the doped silicon layer may either be a poly-silicon or amorphous silicon. Also, the hard mask layer may be silicon oxynitride or one of a number of materials having similar properties. Additionally, the hard mask layer may serve as an anti reflective coating (ARC).
The above summary of the present invention is not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follows.


REFERENCES:
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5441914 (1995-08-01), Taft et al.
patent: 6258727 (2001-07-01), Maccagnan
patent: 6399515 (2002-06-01), Tao et al.

Affiliated with

Also associated with

Rating

Hard mask process to control etch profiles in a gate stack does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hard mask process to control etch profiles in a gate stack, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hard mask process to control etch profiles in a gate stack will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2993082