Handling errors in the C bit of a storage key

Details Handling errors in the C bit of a storage key Handling errors in the C bit of a storage key

1988-11-28

1990-04-10

Atkinson, Charles E.

Excavating

3642653, 3642663, 3642665, 3649581, 371 13, G06F 1110, G06F 1130, G06F 1212, G06F 1216

Patent

active

049167030

ABSTRACT:
A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

REFERENCES:
patent: 4514847 (1985-04-01), Tateishi et al.
patent: 4658356 (1987-04-01), Shiozaki et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 5, 10/78, p. 2008, "Replacement of SSK Instruction in a Paging Environment", R. S. Burchi et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 6, 11/79, pp. 2380-2381, "Prevention of Unnecessary Machine Checks Caused by Reference and Change Bit Parity Errors", S. G. Hogan et al.
IBM System/370 Extended Architecture Principles of Operation, Publication No. SA22-7085-1.

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