Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Patent
1994-06-08
1995-08-22
Heyman, John S.
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
368201, 377 38, 377107, H03K 2108, G04F 1004
Patent
active
054446740
ABSTRACT:
The hand held decimal timer circuit comprises: a power supply having a positive voltage output and a ground or common output; a counter circuit coupled to the power supply; a frequency divider circuit coupled to the counter circuit and to the power supply; a clock circuit including an oscillator coupled to the frequency divider circuit; a display circuit coupled to the counter circuit; a switch circuit coupled to the counter circuit; and, the frequency divider circuit including: (a) a first input for receiving a clock signal from the clock circuit, (b) a second input and a third input for receiving, respectively, a positive voltage reference and a ground voltage reference from the power supply, (c) a 12 bit binary counter which counts the clock cycles from the clock circuit and outputs, on a plurality of output pins, a number of clock cycles in binary form, (d) a pair of NAND gates each having at least three inputs and an output, the inputs being coupled to at least some of the plurality of output pins for receiving, directly and through one or more jumpers between selected ones of the output pins, a number of clock signals, (e) a NOR gate having an output and inputs which are operably coupled to the outputs of the pair of NAND gates for generating a reset signal at the output thereof for resetting the number of clock signals, (f) a capacitor coupled between the NOR gate output and ground for coupling the reset signal to the ground reference voltage to insure the 12 bit binary counter is properly reset when power is applied to the second and third inputs of the frequency divider circuit, (g) an inverter gate having an output and an input operably connected to the output of the NOR gate for generating a count signal at the output of the inverter, and (h) the frequency divider circuit having an output for outputting the count signal; and wherein the frequency of the count signal can be configured to count in one of decimal hours and decimal minutes dependent upon the jumpers connected to which selected ones of the plurality of output pins.
REFERENCES:
patent: 3202837 (1965-08-01), Baracket
patent: 3945194 (1976-03-01), Gollinger
patent: 4185452 (1980-01-01), Ikeda
patent: 4199726 (1980-04-01), Bukosky et al.
patent: 4413350 (1983-11-01), Bond et al.
patent: 4596027 (1986-06-01), Bernardson
Heyman John S.
Vigil Thomas R.
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