Hall effect element aligned to reduce package-induced offsets

Surgery – Truss – Pad

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357 25, 357 27, 128789, H01L 2904, H01L 2722, H01L 2966, H01L 2982

Patent

active

051191660

ABSTRACT:
Disclosed is a Hall effect element formed in a single crystal semiconductor chip with the direction of bias current flow aligned parallel with the <100> cyrstallographic direction and also parallel with edges of the chip. The orientation described is selected to minimize piezoresistive effects produced by packaging-induced physical stress on the semiconductor chip.

REFERENCES:
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patent: 4315273 (1982-02-01), Yamamoto et al.
patent: 4317126 (1982-02-01), Gragg, Jr.
patent: 4423434 (1983-12-01), Komatsu
patent: 4673964 (1987-06-01), Popovic et al.
patent: 4739381 (1988-04-01), Miura et al.
Kanda et al "Silicon Hall-Effect Power IC's for Brushless Motors" IEEE Transactions on Electron Dev. vol. ED-29 (1) (Jan. 1982) pp. 151-154.
Kanda "A Graphical Representative of the Piezoresistance Coefficients in Silicon" IEEE Transac. on Electron Dev. vol. ED`29 (1) (Jan. 1982).
Kanda et al "Effect of Mechanical Stress on the Offset Voltages of Hall Devices in Si IC" Phys. Stat. Sol.(a) vol. 35:K115 (1976).
Tuft and Long et al "Recent Developments in Semiconductor Piezoresistive Devices" Solid State Electronics vol. 6 p. 23 (1963).

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