Facsimile and static presentation processing – Static presentation processing – Attribute control
Reexamination Certificate
1999-11-09
2003-01-28
Williams, Kimberly A. (Department: 2622)
Facsimile and static presentation processing
Static presentation processing
Attribute control
C358S534000, C358S535000, C358S530000, C358S003130, C358S003050
Reexamination Certificate
active
06512596
ABSTRACT:
TECHNICAL FIELD
This invention concerns high performance color printers which typically use page-width drop-on-demand inkjet printheads. In particular it concerns a halftoner/compositor unit for digitally halftoning a contone color layer to bi-level, and compositing a black layer over the halftoned contone layer. In another aspect it concerns a method of halftoning and compositing.
SUMMARY OF THE INVENTION
The invention is a halftoner/compositor unit for halftoning a contone color layer to bi-level, and compositing a black layer over the halftoned contone layer, comprising:
An input port to receive an expanded contone color layer in the form of a series of contone color pixel values, and an expanded black layer in the form of a series of black dot values.
A dither unit to dither each contone color pixel value received at the input port and determine the value of a bi-level output dot for each color component.
A composite unit to receive the values of the bi-level output dots from the dither unit and the black dot values from the input port, and to composite the black layer over the halftoned layer, for instance, such that when the value of a black dot represents full opacity, then the values of the halftoned dots for each color are set to represent no color.
A clock enable generator to generate enable signals for clocking the contone color pixel input, the black dot input, and the dot output.
An output port to deliver a set of bi-level image lines in the form of a series of bi-level dots, which may have the color planes separated.
The output may be a set of 1600 dpi bi-level image lines.
The color contone layer may be a CMYK contone layer.
An input contone CMYK FIFO may include a full 8 KB line buffer. Each line is read once and then used contone scale factor times to effect vertical up-scaling via line replication. FIFO write address wrapping is disabled until the start of the final replicated use of the line, at which time the clock enable generator generates a contone line advance enable signal which enables wrapping.
An alternative is to read the line from main memory contone scale factor times, increasing memory traffic by 65MB/s, but avoiding the need for the on-chip 8 KB line buffer.
The consumer of the data produced by the unit is typically a printhead interface. The printhead interface may not only require bi-level image data in planar format, i.e. with the color planes separated. But, it may also require that even and odd pixels are separated. When the color contone layer is a CMYK contone layer the output stage of the unit may use 8 parallel pixel FIFOs, one each for even cyan, odd cyan, even magenta, odd magenta, even yellow, odd yellow, even black, and odd black.
For this purpose the clock enable generator may also generate an even signal which is used to select the even or odd set of output dot FIFOs.
Once started, the unit may proceed until it detects an end-of-page condition, or until it is explicitly stopped via its control register.
The unit generates a page of dots of a specified width and length and a number of registers may be employed to provide data to control the page structure and parameters.
A page width register to receive page width data which may correspond to the width of the printhead.
A page length register to receive page length data which may correspond to the length of the target page.
A left margin register to receive data describing the position of the left margin.
A right margin register to receive data describing the position of the right margin.
The distance from the left margin to the right margin corresponds to the target page width. The halftoner/compositor unit generates target page data between specified left and right margins relative to the page width.
A black page width register to receive data describing the black page width.
A contone page width register to receive data describing the contone page width.
The halftoner/compositor unit consumes black and contone data according to specified black and contone page widths.
The halftoner/compositor unit clips black and contone data to the target page width. This allows the black and contone page widths to exceed the target page width without requiring any special end-of-line logic at the input FIFO level.
For this purpose the clock enable generator may also generate a margin signal which is used to generate white dots when the current dot position is in the left or right margin of the page.
The halftoner/compositor unit scales contone data to printer resolution both horizontally and vertically based on a specified scale factor. A contone scale factor register may be provided to receive a contone scale factor. This scale factor must be written to the contone scale factor register prior to starting the halftoner/compositor unit.
The halftoner/compositor control and configuration registers may be summarised according to the following table:
Halftoner/compositor control and configuration registers
register
width
description
start
1
Start the halftoner/compositor.
stop
1
Stop the halftoner/compositor.
page width
14
Page width of printed page, in dots. This is the
number of dots which have to be generated
for each line.
left margin
14
Position of left margin, in dots.
right margin
14
Position of right margin, in dots.
page length
15
Page length of printed page, in dots. This is the
number of lines which have to be generated
for each page.
black page width
14
Page width of black layer, in dots. Used to
detect the end of a black line.
contone page
14
Page width of contone layer, in dots. Used to
width
detect the end of a contone line.
contone
4
Scale factor used to scale contone data to
scale factor
bi-level resolution.
In the dither cell each dot column of the volume can be implemented as 256 separate bits.
Alternatively, each dot column of the volume can be implemented as a fixed set of thresholds. Using three 8-bit thresholds, for example, only consumes 24 bits. Now, n thresholds define n+1 intensity intervals, within which the corresponding dither cell location is alternately not set or set. The contone pixel value being dithered uniquely selects one of the n+1 intervals, and this determines the value of the corresponding output dot.
The contone data may be dithered using a triple-threshold 64×64×3×8-bit (12 KB) dither volume. The three thresholds form a convenient 24-bit value which can be retrieved from the dither cell ROM in one cycle.
If dither cell registration is desired between color planes, then the same triple-threshold value can be retrieved once and used to dither each color component.
If dither cell registration is not desired, then the dither cell can be split into four subcells and stored in four separately addressable ROMs from which four different triple-threshold values can be retrieved in parallel in one cycle. Four color planes share the same dither cell at vertical and/or horizontal offsets of 32 dots from each other.
A multi-threshold dither unit may be used. For example, a triple-threshold unit converts a triple-threshold value and an intensity value into an interval and thence a one or zero bit. The triple-thresholding rules are shown in the following Table.
Triple-thresholding rules
interval
output
V ≦ T
1
0
T
1
< V ≦ T
2
1
T
2
< V ≦ T
3
0
T
3
< V
1
The composite unit composites a black layer dot over a halftoned CMYK layer dot. If the black layer opacity is one, then the halftoned CMY is set to zero.
Given a 4-bit halftoned color C
c
M
c
Y
c
K
c
and a 1-bit black layer opacity K
b
, the composite logic is as defined in the following Table:
Composite logic
color channel
condition
C
C
c
K
b
M
M
c
K
b
Y
Y
c
K
b
K
K
c
K
b
The clock enable generator uses a set of counters. The internal logic of the counters is defined in the following Table:
Clock enable generator counter logic
load
decrement
counter
abbr.
w.
data
condition
condition
dot
D
14
page width
RP
a
EOL
b
(D>0)
clk
line
L
15
page length
RP
(L>0)
EOL
left margin
LM
14
left margin
RP
&ens
Silverbrook Research Pty Ltd
Williams Kimberly A.
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