Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-06-30
2001-10-02
Chow, Dennis-Doon (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S063000, C345S067000, C345S589000
Reexamination Certificate
active
06297788
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a half tone display method of a display panel of a matrix display system such as plasma display panel (hereinafter, referred to as a PDP), liquid crystal display panel (LCD), or the like.
2. Description of Related Art
As one of display panels of the matrix display system, a PDP of an AC (alternating current discharge) type is known.
The AC type PDP has: a plurality of column electrodes (address electrodes); and a plurality of row electrode pairs which are arranged so as to perpendicularly cross the column electrodes and in which one scanning line is formed by one pair. Each row electrode pair and column electrode are coated with a dielectric material layer for a discharge space and have a structure such that a discharge cell corresponding to one pixel is formed by a crossing point of each row electrode pair and column electrode.
As one of methods of gradation displaying the display panel of the matrix display system, there is known a method (what is called a subframe method) whereby a display period of time of one frame (one field) is divided into N subframes (subfields) which are lit up for only the time corresponding to a weight of each bit digit of pixel data of N bits and a display is performed.
According to the subframe method, for example, in the case where the pixel data consists of six bits, the display period of one frame is divided into six subframes SF
0
, SF
1
, . . . , and SF
5
. In this instance, in the subframes SF
0
to SF
5
, for example, sustain discharge light emissions of 1 time, 2 times, 4 times, 8 times, 16 times, and 32 times are sequentially executed in this order. By executing one cycle of the light emission by the six subframes, a 64-gradation display for an image of one frame (one field) can be performed. Each subframe is constituted by: a resetting period of once initializing all of the discharge cells; an address period of selecting light-up cells and light-off cells by performing an address scan (data writing) based on the image data; and a sustain discharge period of sustaining a discharge light emitting state for only the light-up cells by supplying a discharge sustain pulse. The sustain discharge period of time is determined by the number of times of the sustain discharge light emission as mentioned above.
In the case that selective writing address method is employed as the address scanning scheme, at first all of the discharge cells are once reset-discharged and wall charges are formed in the resetting period and, after that, all of the cells are driven to the state of discharge light emission and initialization is performed by erasing the wall charges. Subsequently, in the address period of time, only the relevant discharge cells are selectively excited to cause the discharge light emission in accordance with the image data and the wall charges are formed. In this case, the discharge cells in which the wall charges are formed are selected as light-up cells and the discharge cells in which no wall charge is formed are selected as light-off cells.
In the case of using a selective erasing address method, at first all of the discharge cells are once reset-discharged in the resetting period of time and wall charges are formed and initialized. Subsequently, in the address period of time, the wall charges which were once formed are selectively erased and discharged in accordance with the image data, thereby erasing the wall charges. The discharge cells in which the wall charges were erased are selected as the light off cells and the discharge cells in which the wall charges remain as they are are selected as the light up cells.
According to the gradation display method, the light emitting order of the subframes SF
0
to SF
5
in one frame (one field) is fixed to a descending order from the longest light emitting period of time (the number of times of light emission) or an ascending order from the shortest light emitting period.
OBJECTS AND SUMMARY OF THE INVENTION
The invention is made to solve the above problems and it is an object of the invention to provide a half tone display method of a display panel which can prevent the generation of a flicker or a pseudo outline and can improve a contrast and a display picture quality.
According to the invention, there is provided a half tone display method of a display panel in which when light emission driving a display panel having a plurality of row electrodes arranged in the horizonal direction in correspondence with display lines and a plurality of column electrodes which are arranged in the vertical direction which crosses the row electrodes and form discharge cells at crossing points, a unit display period is divided into a plurality of divided periods and light emitting periods of the discharge cells which are executed in the respective divided periods are made different from each other, thereby performing a half tone display, wherein a plurality of light emitting modes in which the orders of the light emitting periods which are allocated to the divided periods are made different from each other are switched and executed every discharge cell or every discharge cell block in which a plurality of adjacent discharge cells constitute a set.
REFERENCES:
patent: 5854540 (1998-12-01), Matsumoto et al.
patent: 5874932 (1999-02-01), Nagaoka et al.
patent: 5907316 (1999-05-01), Mikoshiba et al.
patent: 5940142 (1999-08-01), Wakitani et al.
patent: 6040819 (2000-03-01), Someya
patent: 6052101 (1998-12-01), Moon
patent: 6069610 (1999-02-01), Denda et al.
Honda Hirofumi
Saegusa Nobuhiko
Shigeta Tetsuya
Awad Amr
Chow Dennis-Doon
Morgan & Lewis & Bockius, LLP
Pioneer Electronic Corporation
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