Multiplex communications – Wide area network – Packet switching
Patent
1992-03-16
1994-04-05
Safourek, Benedict V.
Multiplex communications
Wide area network
Packet switching
3701053, 375119, H04J 306
Patent
active
053011961
ABSTRACT:
A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the rate of the incoming data. These clocks are sampled by a pair of edge triggered flip-flops using the transitions of the received data as triggers. The outputs of these flip-flops are exclusive OR-ed to provide a signal indicating whether the generated clock leads or lags the received data. The half-speed 1:2 demultiplexer circuit uses the rising and falling edges of a half-speed 90-degree clock to latch the received data through a pair of flip-flops. The outputs of these flip-flops, each triggered by a different edge of the clock, make up two demultiplexed data streams. The clock recovery and demultiplexer circuits of the present invention can be extended to operate at lower clock rates and configured to provide wider demultiplexing.
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Ewen John F.
Widmer Albert X.
International Business Machines - Corporation
Patel Ajit
Safourek Benedict V.
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