Electric power conversion systems – Current conversion – Using semiconductor-type converter
Reexamination Certificate
2000-07-27
2001-07-31
Berhane, Adolf Deneke (Department: 2838)
Electric power conversion systems
Current conversion
Using semiconductor-type converter
Reexamination Certificate
active
06269014
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a half-bridge configuration containing a first and a second transistor, where the two transistors are connected in series by their path electrodes. An operating voltage is present across the series circuit, and a load can be connected to the path electrodes of the two transistors, the path electrodes being connected to one another.
In order to be able to supply a load, e.g. an electric motor, with a bidirectional current for counterclockwise and clockwise rotation, a so-called H bridge configuration is used. An H bridge configuration is a bridge circuit containing four semiconductor switches, for example 4 MOSFETs, in which the load is located in the shunt path, and two transistors are connected in series by their path electrodes in each bridge path. A drive circuit enables the transistors to be controlled in such a way that the current flows through the load, e.g. the above-mentioned electric motor, in one direction or in the opposite direction. Depending on the current direction, the electric motor rotates in the clockwise or counterclockwise direction.
U.S. Pat. No. 5,703,390 discloses a semiconductor circuit configuration in which four MOSFETs which form a bridge are seated in an electrically insulated manner on an Si support. If large power switches are required in order to switch high currents, however, it is more cost-effective to distribute the power switches between a plurality of supports that are optimized in a function-specific manner.
Published, European Patent Application EP 0 809 292 A2 describes a power transistor module in which two transistors are disposed on a special electrically insulating substrate seated on a metal support. The two transistors are disposed in the above-mentioned half-bridge configuration.
The H bridge configuration disclosed in U.S. Pat. No. 5,703,390 and the half-bridge configuration disclosed in the Published, European Patent Application EP 0 809 292 A2 have the disadvantage that the electrical conductivity and the thermal conductivity are not optimal.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a half-bridge configuration which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the electrical conductivity and the thermal conductivity are as optimal as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a half-bridge configuration, containing a load and two transistors having path electrodes, including a first transistor with a path electrode and a second transistor with a path electrode. The first transistor is connected in series with the second transistor by the path electrodes being connected to one another and defining a series circuit. An operating voltage can be impressed across the series circuit and the load is connected to the path electrodes of the two transistors. The two transistors are of opposite conductivity types and are formed as chips each having a rear side. A common electrically conductive support receives and supports the rear side of each of the chips such that the path electrode of the first transistor is connected to a same one of the path electrode of the second transistor. The common electrically conductive support forms a summation point, and the load is connected to one of the common electrically conductive support and the summation point.
The invention achieves the object by virtue of the fact that the two transistors are of opposite conductivity types, that each transistor is realized on a chip, and that the rear sides of the two chips are seated on a common electrically conductive support. This results in that the path electrode of the first transistor is connected to the same path electrode of the second transistor, and the conductive support forms a summation point, and that the load can be connected to the conductive support or to the summation point.
Each transistor is realized on a chip. Since, in the half-bridge configuration according to the invention, owing to the use of transistors of opposite conductivity types, in contrast to the known half-bridge configurations, identical path electrodes—the collectors or the emitters or, in the case of FETs, the drain electrodes or the source electrodes—rather than non-identical path electrodes are connected to one another. The rear sides of the two chips can be directly connected to one another, because they realize the same path electrodes. According to the invention, this connection is realized by virtue of the fact that the rear sides of the two chips are seated on a common electrically conductive support, e.g. made of metal. Optimum electrical and also thermal connection and conductivity for heat dissipation purposes are attained by the measure of placing the two chips on a common electrically conductive support.
In accordance with an added feature of the invention, the first transistor is a P-MOS field-effect transistor, the second transistor is an N-MOS field-effect transistor, and the path electrodes are drain electrodes. The drain electrode of the second transistor is connected to the drain electrode of the first transistor and to the common electrically conductive support.
In accordance with an additional feature of the invention, there is a drive circuit for generating control signals for controlling the two transistors. The two transistors each having a gate electrode connected to the drive circuit.
In accordance with another feature of the invention, the drive circuit is a chip disposed in an electrically insulated manner on one of the two transistors.
In accordance with another added feature of the invention, the chip forming the drive circuit is seated on that transistor of the two transistors which has a higher impedance. One of the two transistors is a P conductivity type and the chip forming the drive circuit IC is seated on the one of the two transistor of the P conductivity type.
In accordance with another additional feature of the invention, the common electrically conductive support is seated on the load for attaining an optimum electrical and thermal connection.
In accordance with a further added feature of the invention, the load has a first terminal and a second terminal, and in an unidirectional operation the second terminal of the load is connected to one of the operating voltage and ground.
In accordance with a further additional feature of the invention, the two transistors are constructed using vertical technology.
In accordance with yet another feature of the invention, there is a temperature monitoring circuit integrated in the chip forming the drive circuit for protecting the half-bridge configuration against destruction.
In accordance with a concomitant feature of the invention, there is a third transistor; and a fourth transistor connected in series with the third transistor and defining a further summation point at a connection point of the third transistor to the fourth transistor. The second terminal of the load is connected to the further summation point providing a bidirectional operation.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a half-bridge configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
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patent: 4969020 (1990-11-01), Matsushita et al.
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patent: 5631487 (1997-05-01), Hattori
patent: 6055148 (2000-04-01), Grover
Auer Frank
Gantioler Josef-Matthias
Sander Rainald
Xu Chihao
Berhane Adolf Deneke
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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