Half-bridge circuit

Details Half-bridge circuit Half-bridge circuit

2002-08-23

2003-08-12

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S424000

Reexamination Certificate

active

06605976

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to control circuitry, and more particularly to a half-bridge circuit.
BACKGROUND OF THE INVENTION
Bridge circuits are known in the art, and typically serve to convert a direct voltage into a high-frequency alternating voltage. Applications for high voltage half-bridge circuits include electronic ballasts for gas discharge lamps, switched mode power supplies, motor drives, DC-AC converters, and plasma display panel (PDP) drivers. In principle, a bridge circuit is composed of two switches which are connected in series between a high and a low supply voltage and are operated in push-pull to connect an output terminal alternately to the high and the low supply voltage. Where there is only one branch of switches, the circuit is a half-bridge circuit. With a half-bridge circuit half of the supply voltage is available for a resistive/inductive load, or the full supply voltage is available the load is capacitive, as in PDP display drivers. In a typical half-bridge circuit, the switches are field-effect transformers (FETs), such as n-type channel MOS transistors. The source of the low-side transistor and the drain of the high-side transistor are connected to the negative and the positive direct voltage supply, respectively. The drain of the low-side transistor and the source of the high-side transistor are both connected to an output terminal. The source of an inverter, also an n-type channel MOS transistor, is connected to the negative supply.
When a positive control signal is applied to the gate of the inverter transistor, the inverter transistor becomes conducting, the gate of the low-side transistor is connected to the low direct voltage (ground), and the low-side transistor is non-conducting. The high-side transistor is being “driven” in that the positive control signal is applied to the gate of the high-side transistor, which then becomes conductive. The output terminal is at the low level. Alternatively, a low control signal can be supplied to the gate of the inverter transistor and to the high-side transistor so that these transistors are non-conducting. In this case, the low-side transistor is being driven.
In either case, the normal logic supply voltage is too low to efficiently drive transistors. For example the threshold voltage is 1.5V, and the typical transistor driver supplies a gate-source voltage Vgs=10V. As Vgs increases, the conductivity of the transistor can increase greatly.
The upper or high-side transistor can be triggered by referencing the high voltage supply. However, the potential between the source of the high-side transistor to the high voltage supply is subject to variations as the states of other transistors in the circuit change. Existing circuit configurations compensate for these variations by employing a bootstrap circuit consisting of a diode, a capacitor, a resistor, and a 15V auxiliary voltage supply. The bootstrap circuit is established between the output terminal and the gate of the high-side transistor, thereby raising the potential almost 15V above the supply voltage. The bootstrap circuit also enables a current flow through the inverter, and provides a time delay so that the high-side and low-side transistors cannot simultaneously conduct, as the upper transistor may be subject to spurious triggers due to transients at the output terminal.
In one approach, the auxiliary voltage is derived via a resistor from the high direct voltage. The problem with this approach is increased circuit temperature, which indicates an unacceptable level of power dissipation. In order to reduce the current and associated dissipation, an additional switch can be added.
In high-current power semiconductors, the auxiliary voltage is generated by providing a negative voltage to the high-side transistor. A disadvantage of this approach is that the addition of separate transformers or transformer coils for each output phase of the inverter is required.
SUMMARY OF THE INVENTION
There is a current need for an improved configuration of a half-bridge circuit that overcomes the limitations inherent in existing bootstrap circuits by reducing power dissipation without requiring the provision of an auxiliary voltage supply. To this end, the invention provides a half-bridge circuit as defined by any of the independent claims. The dependent claims define advantageous embodiments.
The bridge circuit of the present invention fulfills the need described above by providing a half-bridge driver where either the low-side transistor, the high-side transistor, or both are driven by a “charge trap” which eliminates the need for an additional medium voltage auxiliary supply and eliminates spurious triggering of the high-transistor, thereby restraining power dissipation. This driver is preferably a high voltage integrated circuit.
Briefly, a preferred embodiment of the present invention is a half-bridge circuit that includes an upper and a lower transistor, both of which are high-voltage double-diffused MOSFETs (HV DMOS). The upper transistor is connected at its source to an output terminal, and at its drain to a terminal or rail to which a high direct voltage has been applied. As an example, the lower transistor is n-type, and is connected at its source to a low voltage rail (essentially, to ground), and at its drain to the same output terminal. A capacitive load element is also connected from the output terminal to the low voltage rail. In the exemplary embodiment of this invention, a control circuit provides the control signal that drives the upper transistor, and a second control circuit provides the control signal that drives the lower transistor. This second control circuit is a charge trap, which includes a third field-effect transistor connected at its drain to the output terminal, and at its source to the anode of a diode. The cathode of the diode is connected to the gate of the lower transistor. The second control circuit also includes a fourth field-effect transistor connected at its drain to the gate of the lower transistor and at its source to the low voltage rail, paralleled with a zener diode connected at its anode to the low voltage rail. The zener diode limits the voltage applied to the gate of the lower transistor to a safe level.
Another embodiment of the present invention provides a charge trap control circuit for the upper transistor. The upper control circuit includes a fifth field-effect transistor connected at its drain to the gate of the upper transistor and at its source to the low voltage rail; a sixth field-effect transistor connected at its drain to the low voltage rail and at its source to the anode of a second diode; and a second voltage-limiting zener diode connected at its anode to the source of the upper transistor and at its cathode to the gate of the upper transistor.
An aspect of the present invention is that the upper and the lower charge trap control circuits may be used in tandem in one half-bridge circuit, or individually with other control circuits.
All of the transistors in the above-described embodiments of this invention are field-effect transistors (FET). However, it will be clear without further explanation from the following description that the invention can be used both in full bridge circuits and in half-bridge circuits, and with transistors with similar characteristics including other MOS-type transistors and bipolar transistors such as the insulated gate bipolar transistor (IGBT).
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become more apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention.


REFERENCES:
patent: 5631588 (1997-05-01), Bertolini
patent: 5886563 (1999-03-01), Nasila
patent: 6504316 (2003-01-01), Ito et al.
patent: 6538279 (2003-03-01), Blanchard

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