H-sync to pixel clock phase detection circuit

Details H-sync to pixel clock phase detection circuit H-sync to pixel clock phase detection circuit

1996-12-18

1998-10-20

Burgess, Glenton B.

Television

Synchronization

Automatic phase or frequency control

348537, 348540, 375362, H04N 754

Patent

active

058254315

ABSTRACT:
An H-sync to pixel clock phase detection circuit comprising: a programmable delay line for delaying an H-sync signal; a differential clock driver circuit for producing a pixel clock signal and a pixel clock/signal from a pixel clock signal input; a first D flip-flop having D and CLK inputs and a Q output; a second D flip-flop having D and CLK inputs and a Q output; wherein the delayed H-sync signal from the programmable delay line is applied to the respective D inputs of the first and second D flip-flops, wherein the pixel clock signal from the differential clock driver circuit is applied to the CLK input of the first D flip-flop, and wherein the pixel clock/signal from the differential clock driver is applied to the CLK input of the second D flip-flop; and a third D flip-flop having D and CLK inputs and a Q output; wherein the Q output of the first D flip-flop is applied to the D input of the third D flip-flop, wherein the Q output of the second flip-flop is applied to the CLK input of the third D flip-flop; and wherein the Q output of the third D flip-flop is set when the rising edge of H-sync occurs after the rising edge of pixel clock, but before the falling edge of pixel clock.

REFERENCES:
patent: 4532547 (1985-07-01), Bennett
patent: 4959718 (1990-09-01), Bennett
patent: 5455935 (1995-10-01), Taylor
patent: 5539473 (1996-07-01), Kommrusch et al.

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