H configuration write driver circuit with integral component fau

Dynamic magnetic information storage or retrieval – General processing of a digital signal – Head amplifier circuit

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360 68, 360113, G11B 509

Patent

active

061010529

ABSTRACT:
An H configuration write driver circuit is provided which includes integral fault detection circuitry. A load device, such as a magnetic tape recorder write head, is coupled in an H configuration with four drive transistors. A first and second drive transistor are coupled to opposite ends of the load device and produce current flow through the load device in a first direction. A third and fourth drive transistor are coupled to opposite ends of the load device to produce current flow through the load device in the opposite direction. A resistor is coupled in series between each drive transistor and the load device and these resistors serve to determine the time constant of the rise/fall of current through the inductive write head and to limit current flow through a drive transistor in the event of a short circuit condition therein. Voltage measurement nodes are provided in association with each resistor and the voltage at each node is compared to a predetermined reference voltage in order to produce multiple fault detection signals which may be utilized to accurately identify specific component fault conditions within the driver circuit.

REFERENCES:
patent: 3010079 (1961-11-01), Straube
patent: 3037200 (1962-05-01), Mellott
patent: 3927333 (1975-12-01), Furuhashi
patent: 4015290 (1977-03-01), Bowers
patent: 4477846 (1984-10-01), Cottrell et al.
patent: 4489285 (1984-12-01), Sato
patent: 4551772 (1985-11-01), Sliger
patent: 5101153 (1992-03-01), Morong

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