Guess mechanism for faster address calculation in a pipelined mi

Details Guess mechanism for faster address calculation in a pipelined mi Guess mechanism for faster address calculation in a pipelined mi

1991-10-29

1994-08-02

Rudolph, Rebecca L.

Boots, shoes, and leggings

3642551, 3642557, 3642563, 3642552, G06F 1200

Patent

active

053353331

ABSTRACT:
A processor in which instructions and data at logical addresses are mapped onto real memory locations at physical addresses that are translated from the logical addresses by a translation lookaside buffer (TLB) that takes one clock phase to perform this function. The TLB only needs the upper 20 bits of a logical address, which bits correspond to the logical page number, to do the translation to a physical address. The lower 12 bits are not needed until the TLB translation is done. The add of the "base-plus-displacement/offset" usually does not cross a page boundary, that is, the upper 20 bits are the same after the add. A mechanism takes this into account and guesses that the upper 20 bits will not change, and sends them to the TLB. In parallel with the TLB translation, the effective address add of the "base-plus-displacement" is computed. After the add, if the upper 20 bits did not change, then the 20 physical address bits from the TLB plus the lower 12 bits from the address computation are concatenated to produce the complete correct 32-bit physical address. If the upper 20 bits did change due to the actual add then the logical page number (the upper 20 bits) that were given the TLB were wrong. This is detected and a signal is generated that tells the memory side to redo the last memory access, and to use the new 32-bit logical address that was just computed by the effective address-generation hardware.

REFERENCES:
patent: 4622631 (1986-11-01), Frank et al.
patent: 4811206 (1989-03-01), Johnson
patent: 4847748 (1989-07-01), Yamahata et al.

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