Guard ring for reducing pattern sensitivity in MOS/LSI dynamic R

Details Guard ring for reducing pattern sensitivity in MOS/LSI dynamic R Guard ring for reducing pattern sensitivity in MOS/LSI dynamic R

1979-10-11

1986-05-06

Munson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 2311, 357 41, 365149, H01L 2978, H01L 2702, G11C 1124

Patent

active

045875421

ABSTRACT:
An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.

REFERENCES:
patent: 3573509 (1971-04-01), Crawford
patent: 3863065 (1975-01-01), Kosonocky
patent: 4044373 (1977-08-01), Nomiya et al.
patent: 4160985 (1979-07-01), Kamins et al.

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