Guaranteed dynamic pulse generator

Details Guaranteed dynamic pulse generator Guaranteed dynamic pulse generator

1998-01-07

2000-02-22

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

327200, 327208, G11C 800

Patent

active

060288140

ABSTRACT:
The present invention is dynamic pulse generator for generating an output pulse from a first input pulse and a second input pulse, where the output pulse is guaranteed to have a pulse width of at least the pulse width of whichever of the two input pulses has a delayed leading edge with respect to the other. The first input pulse has a first leading edge and a first trailing edge. The second input pulse has a second leading edge and a second trailing edge. The second leading edge is delayed from the first leading edge. An edge detector detects the second leading edge, and outputs a first predetermined level when the second leading edge is detected. The edge detector also detects the first trailing edge and the second trailing edge and outputs a second predetermined level. A latch is responsive to the edge detector and generates a signal indicating that the second leading edge has been detected. The latch maintains the output of the edge detector at the first predetermined level until the edge detector detects both the first trailing edge and the second trailing edge.

REFERENCES:
patent: 5304951 (1994-04-01), Cosand
patent: 5374894 (1994-12-01), Fong
patent: 5633607 (1997-05-01), Millar
patent: 5798730 (1998-08-01), Sanchez
Hitachi, "HM5216326 Series Block Diagram," (Undated), one sheet.
Samsung Electronics, "KM4132G271 Graphic Memory," (1996), p. 1.
NEC Block Diagram, ".mu.PD48150," (undated), 1 sheet.

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