GTO thyristor capable of preventing parasitic thyristors from be

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor

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257122, 257124, 257128, 257132, 257135, 257147, 257152, 257153, 257163, 257167, H01L 2974, H01L 2702, H01L 2910

Patent

active

052987698

ABSTRACT:
A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET. A thyristor having such a configuration can effectively prevent a latched-up condition caused by parasitic transistors or thyristors to ensure turn off operations of the host thyristor.

REFERENCES:
patent: 4760431 (1988-07-01), Nakagawa et al.
patent: 4967255 (1990-10-01), Bauer et al.
patent: 5105244 (1992-04-01), Bauer
patent: 5144400 (1992-09-01), Bauer
Baliga, Proceedings of 1990 International Symposium on Power Semiconductor Devices & ICs, pp. 117-121. "The MOS-Gated Emitter Switched Thyristor".

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