Multiplex communications – Duplex – Communication over free space
Reexamination Certificate
2000-08-22
2004-06-29
Nguyen, Hanh (Department: 2662)
Multiplex communications
Duplex
Communication over free space
C370S345000, C370S336000, C370S509000, C455S450000
Reexamination Certificate
active
06757261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to time division multiple access (TDMA) communication systems, such as Global System for Mobile (GSM) transceivers, and in particular, to GSM transceivers capable of receiving General Package Radio Service (GPRS) data.
2. Description of the Related Art
As is well known, GSM is a second-generation cellular communication system standard that was developed to solve problems associated with the original analog cellular communication systems in Europe. GSM uses digital communication techniques, including frequency division duplexing (FDD) and a combination of time division multiple access (TDMA) and frequency division multiple access (FDMA) techniques to allow simultaneous access by base stations to multiple users.
Referring to
FIG. 1
, each communication channel in a GSM system is accessed on a time shared basis and is divided into time frames, which are 4.615 milliseconds long. Each time frame is divided into eight time slots
0
-
7
, each of which is approximately 577 microseconds long. During normal used, i.e., during voice transmission and reception, the digitized voice information is packetized and transmitted during different time slots. For example, a receive operation for accepting incoming voice data may take place during time slot
0
, while a transmit operation for sending voice data may take place during time slot
3
. Additionally, a monitor function may be performed, e.g., during time slot
6
, during which the signal strength for signals arriving from different base stations is monitored for power level. It is necessary to separate these active time slots
0
,
3
,
6
by two or more unused time slots so as to allow the common, or shared, phase lock loop (PLL) within the GSM handset to be set up and locked at the correct frequency for the receive, transmit or monitoring function. Minimum set up and lock times are required due to the use of integer PLL circuits. These integer PLL circuits are generally preferred over fractional PLL circuits since they are less complex and hence require significantly less integrated circuit area and less DC power.
Referring to
FIG. 2
, the transmit and receive functions of a GSM handset can be implemented using conventional transmitter and receiver circuit architectures. In this example, such functions can be implemented in an integrated form using a circuit
100
such as the LMX3411 manufactured by National Semiconductor Corporation of Santa Clara, Calif. As discussed in more detail below, this transmitter uses a modulation synthesizer architecture to convert an I/Q baseband representation to the desired transmit frequency. The receiver is a dual conversion receiver with channel selectivity provided by a SAW filter at the intermediate frequency (IF). In this particular integrated circuit
100
, most of the transmitter and receiver functions are integrated within the chip.
Incoming signals received by the antenna
102
are forwarded to the low noise amplifier (LNA) stage
104
, the bias for which is controlled by a control circuit within the chip
100
. A band pass filter stage
106
filters the amplified signal prior to its frequency down conversion in the RF mixer stage
108
which is driven by a local oscillator signal provided by the RF PLL circuit
110
which uses an integer PLL
112
. The resulting IF signal is filtered by an external SAW band pass filter
112
which provides the channel selectivity. The filtered IF signal is then amplified by an IF amplifier
114
having a programmable signal gain.
The amplified IF signal is converted to a quadrature representation in an I/Q mixer stage
116
. The local oscillator signal is provided by the IF PLL circuit
114
which also uses an integer PLL
116
. The resulting I and Q signals are low pass filtered and further amplified in a digitally programmable gain amplifier stage
118
.
The transmitter architecture is based on a closed loop modulation of wide band frequency synthesizer. A wide band PLL
122
modulates an external voltage control oscillator (VCO)
126
having a loop filter bandwidth, as determined by the loop filter
124
, sufficiently wide to correctly track the modulation inserted into the loop. A low pass filter
128
is used to filter out harmonics of the output signal prior to its amplification by the power amplifier
130
and transmission via the antenna
102
. The output signal is also fed back to the transmitter down conversion mixer
118
, which also receives its local oscillator signal from the RF PLL circuit
110
. The resulting IF signal is band pass filtered and converted to a quadrature representation in the transmit quadrature mixer stage
120
in accordance with the outgoing signal data intended for transmission. These I and Q signals are low pass filtered and provided to the wide band PLL
122
, along with the shared signal from the IF PLL circuit
114
.
As discussed in more detail below, the aforementioned control and programming functionality is achieved by a way of an interface and control stage
120
which provides the programmable control data for the various control stages and programmable circuits.
Referring to
FIG. 3
, the interface and control stage
120
includes a set
200
of seven registers
201
-
207
, which are used to store strings of control data ranging from 8 to 24 bits in length. The first register
201
controls power to the various stages of the circuit
100
. The second register
202
provides the gain control information for the various programmable gain stages. The third
203
and fourth
204
registers store the control data for the N-counters within the RF
112
and IF
116
PLL stages (FIG.
2
). The fifth register
205
stores the control data for the R-counters within the PLL stages
112
,
116
. The sixth register
206
stores the control data for the wide band PLL stage
122
. The last register
207
stores miscellaneous control data used for various other functions within the circuit
100
.
While the above-discussed transceiver architecture and control works well for most GSM services, particularly voice transmission and reception, the introduction of data services, such as GPRS, presents a problem concerning the lock time requirement of the PLL circuits. For example, for Class
12
GPRS, the worst case PLL lock time requirement is approximately 200 microseconds when using the above-discussed conventional approach for programming the receiver. In order to achieve this 200 microsecond lock time, the PLL circuits would need to be fractional PLL circuits which require significantly more integrated circuit area and DC power than integer PLL circuits such as those presently used in most cases. This means, that for normal voice operation where this faster lock time is not required, the power consumption of the handset is nonetheless increased significantly.
More specifically, a Class
12
GPRS operation will use up to five of the available eight time slots in a GSM time frame for data communication. For example, four receive slots and one transmit slot may be used, resulting in the following analysis (it will be understood that other permutations of receive and transmit slots may also be used and will yield the same analysis). As is known, a GSM time frame has eight time slots, each of which is approximately 577 microseconds. In this example, four receive operations, one transmit operation and one power monitor operation must be completed within the one time frame. Additionally, the transceiver needs to be set up for the subsequent time frame. Technically, there are two time slots allowed between the end of the receive operation and the beginning of the transmit operation within the time frame. However, since a GSM system is synchronized to the base station, the transmit signal may need to be transmitted prior to the actual start of the time slots within the intended handset so as to ensure that the signal arrives at the base station as the correct time. This is called “timing advance.” The maximum specified timing advance is approximately 232
Olgaard Christian Volf
Yeung Steve
National Semiconductor Corporation
Nguyen Hanh
Vedder Price Kaufman & Kammholz P.C.
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