Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2000-12-29
2004-08-31
Ngo, Ricky (Department: 2661)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S412000, C370S395700
Reexamination Certificate
active
06785271
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a public switch telephone network (PSTN) switching system, and more particularly, to a group switching apparatus of a multi-channel data system capable of performing a multi-channel service.
2. Background of the Related Art
In general, a PSTN switching system provides a multi-channel service by combining at least two channels to accommodate more than 64 Kbps data traffic. In such a case, the generated multi-channel data is processed by mutual interaction between a switch hardware (H/W) (such as a time switch) for switching data by a single channel unit and software (S/W) for controlling and managing the switch H/W.
FIG. 1
is a schematic block diagram of a related art time switch having a single channel switching structure. As shown in
FIG. 1
, the related art time switch includes a speech memory (SM)
10
, a counter
12
, a connection memory (CM)
14
and a processor interface unit
16
.
As a dual port random access memory (DPRAM) for temporarily storing an input time slot (TS), the speech memory (SM)
10
is accessed by a write address (SM_WA) and a read address (SM_RA).
The counter
12
provides the SM
10
and the CM
14
with an access address. The counter
12
counts a system clock signal (CLOCK) that has the same period as the interval of one time slot (TS). If 1024 time slots (TS) are multiplexed in one frame, a count value is sequentially increased from ‘0’ to ‘1023’. The corresponding count value is provided to the write address (SM_WA) of the SM
10
and to the read address (CM_RA) of the CM
14
.
The CM
14
is a DPRAM in which connection information provided by the S/W is stored. Connection data (CM_CD) stored in the CM
14
is read by the CM_RA and then provided to the read address (SM_RA).
The processor interface unit
16
communicates with control S/W of an upper processor (not shown) through a control bus (C-BUS) and records connection information received from the control S/W in the CM
14
.
The multi-channel switching operation of the related art time switch constructed as described above will now be described.
First it is assumed for this example that 1024 time slots (TS) are multiplexed in one frame and a subscriber requests 4-channel service. It is further assumed that four time slots (TS#
4
~TS#
7
) on an input highway (IN_HW) should be switched to four different time slots (TS#
16
~TS#
19
) on an output highway (OUT_HW).
When 4-channel service is requested by the subscriber, the control S/W of an upper processor receives a command from its upper processor (that is, an upper-upper processor) (not shown) that the input time slots (TS#
4
~TS#
7
) are to be switched to the output time slots (TS#
16
~TS#
19
).
Upon receipt of the command, the S/W determines connection formation (CM_CA and CM_CD) to be recorded in the CM
14
as shown in the below Table 1 and outputs them to the processor interface unit
16
through the control bus (C-BUS) four times.
TABLE 1
IN_TS
OUT_TS
CM_CA
CM_CD
TS #4
TS #16
16
4
TS #5
TS #17
17
5
TS #6
TS #18
18
6
TS #7
TS #19
19
7
Accordingly, as shown in
FIG. 3B
, the CM_CD ‘
4
~
7
’ are sequentially recorded in the addresses ‘
16
~
19
’ of the CM
14
by the processor interface unit
16
. Thereafter, in order to check an error for the CM_CD as recorded in the CM
14
, the control S/W sequentially transmits the CM_CA (
16
~
19
) and performs a reading operation of the CM_CD (
4
~
7
) four times.
Meanwhile, with reference to
FIG. 2
, data (!!,@@, ## and $$) of four time slots (TS#
4
~TS#
7
) inputted through the input highway (IN_HW) are sequentially recorded in the SM
10
according to write addresses (SM_WA) ‘
4
~
7
’ as shown in FIG.
3
A.
Thereafter, when an input time of the time slots (TS#
16
~TS#
19
) reaches as time lapses, the read addresses (CM_RA) of the CM
14
are sequentially increased from 16 to 19 by the counter
12
, so that the connection data (4~7) recorded in the addresses
16
~
19
of the CM
14
are read by the CM_RA and outputted to the read address (SM_RA) of the SM
10
.
Accordingly, the time slot data (!!,@@, ##, $$) stored in the addresses
4
~
7
of the SM
10
are sequentially read by the SM_RA (
4
~
7
) and outputted to the output highway (OUT_HW). Thus, the switching operation is performed from the time slots (TS#
4
~TS#
7
) to the time slots (TS#
16
~TS#
19
).
The related art time switch has various problems. For example, it has only a single channel switching structure. Thus, when processing a multi-channel service using the related art time switch, the control S/W must write the channel connection information in the CM as many times as there are channels. In addition, in order to check whether there is an error for the data stored in the CM, the control S/W has to manage connection information of each channel. Specifically, the control S/W must read the connection information from the CM as many times as there are channels. These factors disadvantageously lead to complexity in the control S/W and generation of an excessive amount of management data where the multi-channel service is implemented, resulting in degradation in efficiency in processing the multi-channel service.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to provide a group switching apparatus for multi-channel data that substantially obviates problems caused by disadvantages in the related art.
Another object of the present invention is to provide a group switching apparatus for multi-channel data which performs multi-channel switching using the same controlling operation as the single-channel switching system, thereby improving efficiency of a multi-channel service.
Another object of the present invention is to provide a group switching apparatus for multi-channel data that can provide various multi-channel services without changing the construction of a circuit.
To achieve at least these objects, in whole or in parts, there is provided a group switching apparatus of a multi-channel data including a speech memory (SM) for temporarily storing a time slot to be switched; a connection memory (CM) for storing single connection information; a group connection memory (GCM) for storing group connection information; a counter for counting a system clock signal and outputting a read address for the CM; and address generating unit for converting an output of the counter and generating a read address for the GCM; a processor matching unit for interfacing connection information provided from an upper processor to the CM or GCM; a multiplexer for selectively outputting the output of the CM or the output of the to GCM according to the connection state signal outputted from the GCM; and an adder for adding the output of the counter and the output of the multiplexer and outputting the added value as a read address for the SM.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 4093827 (1978-06-01), Charransol et al.
patent: 4543652 (1985-09-01), Amada et al.
patent: 4941141 (1990-07-01), Hayano
Fleshner & Kim LLP
LG Electronics Inc.
Moore Ian
Ngo Ricky
LandOfFree
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