Group III-V compound semiconductor based heterojuncton...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure

Reexamination Certificate

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C257S197000, C257S566000, C257S563000, C257S564000

Reexamination Certificate

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07576409

ABSTRACT:
A wafer comprising at least one high FtHBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

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English translation (machine) for JP 05-175438.
English translation (machine) for JP 05-175438, Jul. 13, 1993.
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