Group-III nitride semiconductor stack, method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – With heterojunction

Reexamination Certificate

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C257S191000, C257SE33008, C257SE33026, C257SE33048

Reexamination Certificate

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07148518

ABSTRACT:
A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.

REFERENCES:
patent: 5874747 (1999-02-01), Redwing et al.
patent: 6072189 (2000-06-01), Duggan
Iwaya, et al., “Reduction of Etch Pit Density in Organometallic Vapor Phase Expitaxy-Grown GaN on Sapphire by Insertion of a Low-Temperature-Deposited Buffer Layer between High-Temperature-Grown GaN” Jpn.J. Appl. Phys. vol. 37 (1998) pp. 316-318.
Amano, et al., “Stress and Defect Control in GaN Using Low Temperature Interlayers” Jpn.J. Appl. Phys. vol. 37 (1998) pp. 1540-1542).

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