Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2003-02-27
2004-07-20
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S190000, C257S347000, C257S352000
Reexamination Certificate
active
06765241
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a field effect transistor (FET) with a sapphire substrate, in particular to a field effect transistor utilizing a group III nitride semiconductor material such as GaN.
BACKGROUND ART
The group III nitride semiconductors including GaN have carrier transport characteristics close to that of GaAs, together with high breakdown electric fields due to their wide band gaps. They are, thus, regarded as strong candidate materials for high frequency, high power transistors.
When a device is manufactured making use of a GaN based semiconductor material, because it is difficult to obtain a bulk GaN based substrate, there is normally employed a process for fabricating a device wherein a GaN based semiconductor layer is formed by epitaxial growth on a substrate of a different material. For the substrate of a different material, sapphire or SiC is utilized. SiC has an excellent thermal conductivity but also drawbacks of high cost and difficulty to attain a large wafer area. In contrast, although sapphire has an inferior thermal conductivity, the cost can be lowered through the use of a wafer with a larger diameter. In application, therefore, these substrates of different materials are chosen appropriately, according to the occasion and the purpose of use and so forth. In the field of MMICs (Monolithic Microwave Integrated Circuits) or the likes, there are some applications with small electric power in which the restriction for heat diffusion is not strong. In such applications, sapphire rather than SiC is in wide use.
When, using a sapphire substrate, a FET is fabricated, in prior art, a C plane sapphire is utilized and the device is formed on the C plane (Japanese Patent Application Laid-open, No. 82671/2000, Jpn. J. Appl. Phys., Vol. 38 (1999) pp. 2630 (T. Egawa et al.), etc.).
FIG. 5
is a view showing a structure of a conventional MESFET (Metal Semiconductor FET) disclosed in FIG. 12 of Japanese Patent Application Laid-open, No. 82671/2000. Herein, upon a C plane sapphire substrate
51
, a GaN buffer layer
52
and an n-type GaN channel layer
53
are laid, and a source electrode
54
, a gate electrode
55
and a drain electrode
56
are formed thereon. Meanwhile,
FIG. 6
is a view showing a structure of a conventional HEMT (High Electron Mobility Transistor) disclosed in FIG. 13 of the same publication. Upon a C plane sapphire substrate
61
, a GaN buffer layer
62
, an undoped GaN channel layer
63
and an n-AlGaN electron supplying layer
64
are laid, and a source electrode
65
, a gate electrode
66
and a drain electrode
67
are formed thereon. In both of these cases, a GaN based semiconductor layer is laid upon a C plane of sapphire to fabricate a FET. Further, it is described, in that publication, that any plane of sapphire such as an A plane, N plane, S plane, R plane, M plane or the like may be utilized in fabricating an optical device or an electronic device with a sapphire substrate. However, examples specifically disclosed therein are nothing else but the ones of forming a device on a C plane of sapphire, and any specific processes for manufacturing or device design criteria for the cases to utilize any other plane are not described at all.
As described above, in conventional techniques, a GaN based semiconductor layer is formed upon a C plane of sapphire to form a device, which gives rise to the following problems.
First, attempts to obtain a wafer with a larger diameter are subjected to a certain restriction. In recent years, from the point of view of improving the productivity, there have been demands that wafers should have larger diameters. Yet, sapphire whose C plane is chosen as the crystal growth face cannot be readily made to have a larger diameter, because of its low workability through surface polishing due to its poor mechanical processing feasibility and little ability to grow the crystal to have a large width by the ribbon crystal method or the like. A substrate with the largest diameter attained so far is 4 inches in diameter.
Secondly, a heat radiation characteristic thereof is difficult to improve. Since sapphire has a low thermal conductivity, improvements on the heat radiation characteristic have been sought after for some time and, for this purpose, thinner substrates have been looked for. Nevertheless, sapphire has insufficient feasibility in mechanical processing as described above so that a reduction in thickness is hard to achieve and, thus, the heat radiation characteristic is difficult to improve.
Thirdly, parasitic capacitances generated in the substrate are relatively large and act as an inhibitory factor to the improvement of device performance. Especially, in the case of a C plane sapphire, it is necessary to make the substrate have a certain thickness from the point of mechanical processing feasibility, which results in generation of large parasitic capacitances in the substrate.
DISCLOSURE OF INVENTION
In light of the above problems, an object of the present invention is, in a group III nitride semiconductor device, to improve the productivity and heat radiation characteristic and, at the same time, to improve device performance through a reduction in parasitic capacitances.
The present invention relates to a semiconductor device which comprises a group III nitride semiconductor layer formed on a single crystalline sapphire substrate, a source electrode and a drain electrode formed apart from each other on the surface of said group III nitride semiconductor layer, and a gate electrode formed between said source electrode and said drain electrode; wherein
said group III nitride semiconductor layer is formed on a plane which lies parallel to a C axis of said single crystalline sapphire substrate.
The present invention provides a semiconductor device which comprises a group III nitride semiconductor layer formed on a single crystalline sapphire substrate, a source electrode and a drain electrode formed apart from each other on the surface of said group III nitride semiconductor layer, and a gate electrode formed between said source electrode and said drain electrode; wherein
said group III nitride semiconductor layer is formed on a plane lying parallel to a C axis of said single crystalline sapphire substrate; and a thickness of said single crystalline sapphire substrate is not greater than 100 &mgr;m.
Further, the present invention provides a semiconductor device which comprises a group III nitride semiconductor layer formed on a single crystalline sapphire substrate, a source electrode, a drain electrode and a pad electrode formed apart from one another on the surface of said group III nitride semiconductor layer, and a gate electrode formed between said source electrode and said drain electrode; wherein
said group III nitride semiconductor layer is formed on a plane lying parallel to a C axis of said single crystalline sapphire substrate; and a thickness of said single crystalline sapphire substrate t
sub
satisfies the following Equation (1).
t
sub
≦
10
ϵ
sub
S
pad
ϵ
epi
S
gate
t
act
(
1
)
where
S
pad
is an area of the pad electrode;
S
gate
is an area of the gate electrode;
&egr;
sub
is a relative permittivity of the sapphire substrate in the direction of the thickness;
&egr;
epi
is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness;
t
sub
is a thickness of the sapphire substrate; and
t
act
is an effective thickness of the group III nitride semiconductor layer.
Herein, the pad electrode refers to an electrode to supply electricity for a source or a drain from the outside. Further, t
act
(an effective thickness of the group III nitride semiconductor layer) represents a distance from an interface of the gate electrode and the surface of the semiconductor layer to a layer where carriers are present. For instance, in a HEMT, this refers to the distance between the lower end of the gate electrode and the two-dimensional electron gas layer, while, in a MESFET, this refers to the thi
Ando Yuji
Hayama Nobuyuki
Kasahara Kensuke
Kuzuhara Masaaki
Matsunaga Kohji
Dickey Thomas L.
NEC Corporation
Tran Minhloan
LandOfFree
Group III nitride semiconductor device of field effect... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Group III nitride semiconductor device of field effect..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Group III nitride semiconductor device of field effect... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3204709