Group III nitride-based compound semiconductor device

Details Group III nitride-based compound semiconductor device Group III nitride-based compound semiconductor device

2011-05-24

2011-05-24

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With specified crystal plane or axis

C257S094000, C257S103000, C257S201000, C257SE21292

Reexamination Certificate

active

07948061

ABSTRACT:
A characteristic feature of the invention is to form, in a Group III nitride-based compound semiconductor device, a negative electrode on a surface other than a Ga-polar C-plane. In a Group III nitride-based compound semiconductor light-emitting device, there are formed, on an R-plane sapphire substrate, an n-contact layer, a layer for improving static breakdown voltage, an n-cladding layer made of a multi-layer structure having ten stacked sets of an undoped In0.1Ga0.9N layer, an undoped GaN layer, and a silicon (Si)-doped GaN layer, a multi-quantum well (MQW) light-emitting layer made of a combination of In0.25Ga0.75N well layers and GaN barrier layers stacked alternatingly, a p-cladding layer made of a multi-layer structure including a p-type Al0.3Ga0.7N layer and a p-In0.08Ga0.92N layer, and a p-contact layer (thickness: about 80 nm) made of a stacked structure including two p-GaN layers having different magnesium concentrations. Through etching, the n-contact layer having a thickness direction along the c-axis is provided with stripe-patterned microditches each having side walls, which assume a C-plane, whereby ohmic contact is established between a negative electrode and each C-plane side wall.

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Chinese Office Action dated Dec. 25, 2009 and English translation thereof.
Japanese Office Action dated Apr. 6, 2010, with English translation.
Japanese Office Action dated Nov. 10, 2009, for Japanese Patent Application No. 2007-195419 (and partial English translation).

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