Group erasing system for flash array with multiple sectors

Details Group erasing system for flash array with multiple sectors Group erasing system for flash array with multiple sectors

2005-09-06

2005-09-06

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185230

Reexamination Certificate

active

06940759

ABSTRACT:
A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

REFERENCES:
patent: 5920501 (1999-07-01), Norman
patent: 6118705 (2000-09-01), Gupta et al.
patent: 6735126 (2004-05-01), Nakagawa
patent: 6768671 (2004-07-01), Lee et al.

Affiliated with

Also associated with

Rating

Group erasing system for flash array with multiple sectors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Group erasing system for flash array with multiple sectors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Group erasing system for flash array with multiple sectors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3374052