Grounding method to eliminate the antenna effect in VLSI process

Details Grounding method to eliminate the antenna effect in VLSI process Grounding method to eliminate the antenna effect in VLSI process

1993-09-22

1995-07-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437941, H01L 21465

Patent

active

054341086

ABSTRACT:
A method of subjecting an integrated circuit, having electrically grounded elements and large first metal regions on its surface which are connected to device structures, to a plasma process, is described. Large first metal regions are connected to the electrically grounded elements. The integrated circuit is placed in a chamber for accomplishing the plasma process. The integrated circuit is subjected to the plasma process such that the connecting of the large first metal regions to the electrically grounded elements prevents damage to the device structures. The integrated circuit is removed from the chamber. Finally, the large first metal regions are disconnected from the electrically grounded elements.

REFERENCES:
patent: 5041888 (1991-08-01), Possin et al.
patent: 5120680 (1992-06-01), Foo et al.
Shone et al in "Gate Oxide Charging and Its Elimination for Metal Antenna Capacitor and Transistor in VLSI CMOS Double Layer Metal Technology" (published in Symposium on VLSI Technology, pp. 73-74 in Jun., 1988).

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