Coating apparatus – Gas or vapor deposition – With treating means
Reexamination Certificate
1998-05-29
2001-03-20
Mills, Gregory (Department: 1763)
Coating apparatus
Gas or vapor deposition
With treating means
C118S7230IR, C156S345420, C204S192120
Reexamination Certificate
active
06202589
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the manufacture of integrated circuits, and more particularly to etching apparatus for patterning layers of select materials formed upon surfaces of semiconductor wafers.
DESCRIPTION OF RELATED ART
A wafer fabrication process typically forms many identical integrated circuits upon each of several silicon wafers processed as a group (i.e., lot). Each integrated circuit consists of electronic devices electrically coupled by conductive traces called interconnect lines (i.e., interconnects). Interconnects are typically patterned from conductive layers formed on or above the surface of a silicon substrate. One or more conductive layers may be patterned to form one or more levels of interconnects vertically spaced from each other by one or more interlevel dielectric layers. Dielectric-spaced interconnect levels allow formations of densely patterned devices on relatively small surface areas.
Interconnects on different levels are commonly coupled electrically using contact structures formed in holes etched through interlevel dielectric layers separating the interconnects (i.e., vias). Following the formation and patterning of an interconnect level, an interlevel dielectric layer is deposited over the interconnect level. Prior to the formation and patterning of a subsequent interconnect level, vias are etched through the interlevel dielectric layer in locations where interconnects on different interconnect levels are to be connected. Metal via “plugs” are then formed within in the via openings. A via filled with a metallic via plug comprises a contact structure which electrically couples interconnects on different levels.
Vias are preferably substantially vertical openings, and are typically formed using non-isotropic (i.e., anisotropic) plasma (i.e., “dry”) etch techniques. Anisotropic etch techniques etch an exposed material at a greater rate in one direction than any other. An anisotropic etch process which etches an interlevel dielectric layer at a greater rate in the vertical direction is capable of producing vias having substantially vertical side walls.
In a plasma etch process, a glow discharge (i.e., a plasma) is formed when radio frequency (RF) electrical power is applied to reactant gases within a reaction chamber. The reactant gases produce chemically reactive species (atoms, ions, and radicals). These reactive species diffuse to the surface of a material being etched, and adhere to (i.e., are adsorbed upon) the surface of the material. A chemical reaction occurs, with the formation of volatile by-products. These by-products are released (i.e., desorbed) from the surface and diffuse into the ambient.
The above described plasma etch process is substantially a chemical process and removes material at approximately the same rate in all directions (i.e., is an isotropic process). Anisotropic etching requires an etching process having a directional property as described above. Several different etch apparatus operate with a semiconductor wafer placed between two parallel electrodes within the reaction chamber. In such apparatus, an electrical bias may be applied between the parallel electrodes such that energetic ions are directed at an exposed surface of the semiconductor wafer. The directing of the energetic ions adds a significant physical component to the otherwise substantially chemical etch process. When the exposed surface of the semiconductor wafer is parallel to the electrodes, the energetic ions under the influence of the electrical bias strike the surface at an angle normal to the surface (i.e., in the vertical direction). The resulting vertical component of the etch process is capable of forming features (e.g., vias) with substantially vertical side walls.
FIG. 1
is a cross-sectional view of an exemplary etch apparatus
10
currently used for anisotropic etching. Etch apparatus
10
includes a chamber
12
. Etch apparatus
10
may be, for example, an HDP Centura® Model 5300 etch apparatus made by Applied Materials, Inc., Santa Clara, Calif. Chamber
12
includes a wafer chuck
14
for holding a semiconductor wafer
16
in place during processing, and an RF coil
18
for imparting energy to a reactant gas within chamber
12
. A cooling ring
20
forms a removable upper housing of chamber
12
. Cooling ring
20
houses a plate electrode
22
, a heating plate
24
, and a chill plate
26
. Heating plate
24
may include, for example, an electric heating element. Heating plate
24
is used to maintain plate electrode
22
at a desired temperature during processing. Water is circulated through chill plate
26
to cool the exterior surface of cooling ring
20
during use.
Etch apparatus
10
is a parallel-electrode (planar) plasma etch apparatus. Wafer chuck
14
is one of two parallel electrodes, and plate electrode
22
is the other parallel electrode. During use, chamber
12
is held at a ground electrical potential, and wafer chuck
14
is held at a negative electrical potential with respect to chamber
12
. An electrostatic force may be used to hold a backside surface of wafer
16
against a planar upper surface of wafer chuck
14
. A grounding ring
28
electrically couples plate electrode
22
to cooling ring
20
. During processing, cooling ring
20
is physically and electrically coupled to chamber
12
.
During use, chamber
12
is first evacuated via an exit port
30
. One or more reactant gases are then introduced into chamber
12
via an entry port
32
. A first source of RF electrical power is then applied to RF coil
18
, resulting in the ionization of the reactant gases within chamber
12
. A second source of RF electrical power is then applied to wafer chuck
14
while chamber
12
and plate electrode
22
are held at the ground potential. The second source of RF electrical power causes energetic ions to be directed at an exposed frontside surface of semiconductor wafer
16
. The energetic ions strike the frontside surface of wafer
16
at an angle normal to the frontside surface (i.e., in the vertical direction), resulting in the formations of features having substantially vertical side walls.
Prior to placement of semiconductor wafer
16
within chamber
12
, a layer of photoresist material is typically formed upon a frontside surface of wafer
16
over a layer to be patterned (e.g., an interlevel dielectric layer). The layer of photoresist material is then patterned to define the desired features. Remaining portions of the photoresist layer form a mask which protects the underlying portions of the layer to be patterned.
A problem arises when using etch apparatus
10
to form vias in an interlevel dielectric layer. During bombardment of the overlying photoresist layer by energetic ions, organic material is released from the photoresist layer. The organic material forms what is believed to be a polymer layer at the bottoms of the vias. The polymer layer is non-volatile, and often blocks complete removal of the interlevel dielectric material from the vias. Carbon-based polymer materials are poor conductors of electricity, and result in an increase in the electrical resistance of contact structures subsequently formed in the vias. Highly resistive contact structures in critical signal paths of integrated circuits deleteriously reduce the maximum operating speeds of the integrated circuits.
Plate electrode
22
may be made from a material (e.g., silicon) which attracts and holds or “getters” a substantial amount of the organic material derived from the photoresist layer during processing. To adequately perform its gettering function, however, silicon plate electrode
22
must remain substantially electrically grounded.
In at least one commercially available etch apparatus
10
, grounding ring
28
which electrically couples plate electrode
22
to cooling ring
20
is a Monel™ mesh forced into a gap between an outer periphery of silicon plate electrode
22
and an inner surface of cooling ring
20
. Monel™ is a proprietary name for a nickel-copper alloy which is highly resistant to corrosion.
During use, the t
Friede Donald L.
Grahn Stephanie A.
Winters Toby J.
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
Mills Gregory
Powell Alva C
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