Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-09-11
2003-02-25
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06525553
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to the design of a new ground pin that can be used in the singulated Ball Grid Array.
(2) Description of the Prior Art
Quad Flat Packages (QFP) have in the past been used to create surface mounted, high pin count integrated packages with various pin configurations. The electrical connections with these packages are typically established by closely spaced leads that are distributed along the four edges of the flat package. This limits the usefulness of the QFP since a high I/O count cannot be accommodated in this manner. To address this problem, the Ball Grid Array (BGA) package has been created whereby the I/O points for the package are distributed not only around the periphery of the package but over the complete bottom of the package. The BGA package can therefore support more I/O points making this a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mil spacings in a regular or staggered pattern.
The development of the Ball Grid Array (BGA) devices has offered the opportunity to spread device I/O interconnect points over the entire surface of the device, this as opposed to having I/O connect points available only around the periphery of the IC device. Typically, the BGA package is surface mounted and mounted on the surface of a motherboard (a Printed Circuit Board or PCB). The concerns of making reliable I/O interconnects now have shifted from fine pitch in-line lines to contact balls. General sizes that are currently in use for Quad Flat Pack (QFP) packages are a footprint in the 25×25 mm range, a lead pitch of around 0.5 mm while the package itself is about 2 mm thick. A typical ball pitch for a BGA package is around 1.5 mm, with a footprint similar in size to the QFP package and a package thickness similar or slightly less than the thickness of a QFP package.
In order to test a BGA device, the contactor elements of the BGA device are inserted into a contactor plate having a plurality of sock. The contactor plate is coupled to a Device Under Test (DUT) loadboard, which is coupled to a testing machine. The DUT loadboard is in essence printed circuit board that completes electrical connections between the BGA contactor elements via the contactor plate and the tester In order to test the BGA device, the tester sends signals to and receives signal from the BGA device via the electrical conductor paths provided by the contactor plate and the DUT board.
In assembling a BGA package to a PCB, the lower surface of the PC is typically provided with contact balls that connect to an interfacin network of conducting lines that connect to surrounding electrical components or systems. A typical PCB contains two layers of interconnet metal. A cavity is typically formed in the upper surface of the PCB, to semiconductor device that is to be mounted on the PCB is inserted into this cavity. The contact balls of the BGA make electrical contact with the layers of interconnect metal in the PCB, the BGA die is further with bonded to the PCB and enclosed in a molded casing. The operation of with bonding limits the size of the surface on which the wire is connected which in turn increases the size of the die that can be used. The side the BGA that faces the PCB in this arrangement is the backside of the die, heat exchange between the BGA die and the underlying PCB takes place through this interface of the BGA die with the PCB. Since signal lines (in the PCB) are typically of fine construction, these lines do not leave themselves to provide a good path for heat exchange. The heat exchange between the BGA and the PCB must therefore depend on (wider or larger cross section) ground planes in the PCB, which brings with it a limitation on the space that is available to route signal lines in the PCB.
At present the final testing of semiconductor Integrated Circuits performed using Integrated Circuit Handler apparatus whereby each of the IC packages is handled as an individual unit and is advanced to the te socket of the DUT by either gravity feed or by using pick and place methods.
Mass production of semiconductor Integrated Circuits (IC's) bring with it the requirement that these IC's can be tested at high speed. Current trends in the semiconductor industry also promote convenient a bulk handling of semiconductor chips. While high speed testing has bee current practice in the industry for a number of years, this testing i most cases handles individual chips. By mounting individual chips onto strips the flow of chips through the manufacturing and testing cycles be greatly facilitated. This improved capability of handling a larger number of chips has to be accompanied with corresponding improvements the testing capabilities for these chips. Moreover, strip testing also eliminates the use of trays for transportation and storage of individu chips throughout the whole testing process. This results in requiremen for improved capabilities of handling chips that are mounted on strips a testing environment. These improved capabilities transport chips at rapid rate in and out of the test position. While in the test position the chips must be contacted in a rapid and dependable way so that the chip can be tested. This contacting of the chip while the chip is in t position where it can be tested is done by means of probe sockets. The probe sockets are required to rapidly and dependably contact the semiconductor devices under test for the purpose of testing these devices.
During testing of the BGA device, it is important that proper gro connection is provided between the device under test and the test equipment. The ground pin that is provided for this purpose in the present test configuration has a relatively small surface area and is therefore prone to make poor electrical contact between the BGA device and the test equipment. One of the assembly aspects of mounting a BGA device on a PCB is to test the quality of connection that is made in w bonding the BGA device to the PCB. This connection must be a low resistivity connection, which means that the detection of non-stick conditions, whereby the wire bond connection is a high resistivity connection, is required. The relatively small area of the present grou pin presents a relatively too high resistance, which makes the detecti of the non-stick condition difficult and unreliable. The ground pin of the invention addresses this problem by providing a ground pin that allows for good, low resistivity contact between the BGA device and te equipment. The quality of the wire bonding process can therefore be readily monitored.
U.S. Pat. No. 5,604,161 (Barber) shows a semiconductor device assembly with minimized bond finger connections.
U.S. Pat. No. 5,998,228 (Eldridge et al.) shows a method of testing a singulated chip that uses a ground.
U.S. Pat. No. 5,877,552 (Chaing et al.) shows ground pins on a package.
U.S. Pat. No. 5,811,980 (Doyle et al.) teaches a ground pin on a package that contacted by a spring probe/pin. However, this reference differs from invention.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a dependable method of grounding a BGA device during testing of that device.
In accordance with the objectives of the invention a new ground pin is provided for the testing of BGA devices.
REFERENCES:
patent: 5604161 (1997-02-01), Barber
patent: 5672965 (1997-09-01), Kurafuchi et al.
patent: 5811980 (1998-09-01), Doyle et al.
patent: 5877552 (1999-03-01), Chiang
patent: 5998228 (1999-12-01), Eldridge et al.
patent: 6194786 (2001-02-01), Orcutt
patent: 6281693 (2001-08-01), Fukuda
patent: 6288346 (2001-09-01), Ojiri et al.
patent: 6313651 (2001-11-01), Hembree et al.
patent: 6326244 (2001-12-01), Brooks et al.
Lopez Fortunato V.
Reynoso Dexter
Ringor Rufino
Ackerman Stephen B.
Nguyen Jimmy
Saile George O.
Sherry Michael
St Assembly Test Services Ltd.
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