Active solid-state devices (e.g. – transistors – solid-state diode – Punchthrough structure device – Punchthrough region fully depleted at zero external applied...
Reexamination Certificate
2000-06-22
2002-05-14
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Punchthrough structure device
Punchthrough region fully depleted at zero external applied...
C257S497000, C327S078000, C327S535000, C327S536000
Reexamination Certificate
active
06388302
ABSTRACT:
TECHNICAL FIELD
This invention relates to a ground-compatible inhibit circuit structure for integrated circuits that are integrated in a semiconductor substrate which is not referenced to a ground potential. The circuit structure is integrated in the same substrate as an associated circuit to be inhibited, and the substrate is covered with an epitaxial layer which accommodates the components of the inhibit circuit structure.
The invention also relates to a method of providing a ground-compatible inhibit function for integrated circuits that are integrated in a semiconductor substrate unreferenced to ground potential, and, more particularly, the invention is directed toward a circuit structure serving a ground-referred inhibit function in electronic circuits that are integrated in a semiconductor substrate, which is held at a potential other than the ground potential.
BACKGROUND OF THE INVENTION
There are many integrated circuits which include inhibit circuitry accessible from outside of the circuit through an inhibit pin arranged to receive a voltage signal for activating a blocking function in an integrated circuit to be controlled.
There also are many integrated circuits which are formed in a semiconductor substrate that is held at a higher potential than ground. Typical examples of such circuits are certain adjustable voltage regulators whose output is clamped directly to the substrate.
These circuits can be supplied a lower voltage than the voltage applied to the inhibit pin.
Embodiments of this invention encompass all of the integrated electronic circuits that include an inhibit circuit portion but are formed in substrates unreferenced to ground.
As an example, a pre-printed electronic board may be considered, whereon microprocessors are mounted that include at least two supply lines, one at a voltage of 3.3V and the other at a voltage higher than that. An inhibit signal could be delivered to a microprocessor pin over the latter line.
An electronic circuit which is formed in a semiconductor substrate unrelated to ground requires it to be isolated from the substrate. More particularly, since the electronic devices of the integrated circuit are usually formed in an epitaxial layer overlying the semiconductor substrate, the junction between the substrate and the epitaxial layer must be prevented from becoming forward biased and open to a flow of leakage current toward the substrate.
This may be regarded as a minor problem where resistors are to be formed, since it would suffice for the epitaxial layer to be placed at the highest of the potentials available to the integrated circuit.
However, the problem becomes more serious where active components are to be formed, such as bipolar transistors of the NPN type, which have the epitaxial layer for their collector.
Also, the TTL (Transistor Transistor Logic) family of logic circuits must be ensured compatible levels of the signals input to them, and hence of an inhibit signal, where provided.
In this context, a further demand that inhibit circuitry is expected to fill is a capability to operate even when the supply voltage to the circuit to be controlled is below the voltage applied to the inhibit pin.
Shown in
FIG. 1A
herein is a voltage regulating circuit of the adjustable type, which has an output terminal OUT coincident with the P-type substrate of the regulator.
FIG. 1B
shows instead an adjustable regulator having an output OUT which is held at a voltage of 1.25V with respect to ground GND.
Shown schematically in
FIG. 1C
is an adjustable regulator whose output OUT is held at a voltage value being set at 1.25V+1.25*(R
2
/R
1
) by a voltage divider.
The three examples of conventional regulators given above are based on the output OUT being coincident with the P-type substrate. In this way, the output voltage value is allowed to vary within a given range which extends between a zero minimum value and a maximum value equal to the supply voltage, less the minimum voltage drop across the regulator.
Under this condition, therefore, the PN junction between the substrate and the epitaxial layer will never be forward biased.
If a regulator as mentioned above were associated with ground-compatible inhibit circuitry, the problem would arise of how to refer the circuitry to the ground-unrelated substrate. The inhibit circuitry would have to be connected between the power supply and the external ground of the integrated circuit, as shown in
FIG. 2
, in order to have external compatibility ensured for the inhibit function.
The inhibit circuitry shown in
FIG. 2
is to ensure that the PN junction between the substrate and the epitaxial layer, of each of its components, never becomes forward biased, even if the substrate is biased to a maximum value (Vmax technology−min drop), and has a condition of V
INH
>V
supp
.
Operational demands of today's integrated circuits require the inhibit circuitry to meet specifications as listed herein below.
Operating Temperature: −50° C. to +150° C.;
Supply Voltage: 2.75V to Vmax technology (e.g. 30V);
P-substrate Voltage: Vout: 0V to Vmax technology−min drop (where, min drop=VBE+VCEsat);
ON-OFF Voltage, e.g., TTL compatible range:
VthONmax=0.8V,
VthOFFmin=2.0V;
Overall Chip I
13
OFF: <100 &mgr;A;
Maximum Voltage at Inhibit Pin: 7V;
Maximum Current on Inhibit Pin: <30 &mgr;A;
Minimum Hysteresis: 50 mV.
Related schemes for providing inhibit circuitry that would meet the above specifications have proved incapable to prevent the PN substrate/epitaxial junction from becoming forward biased. In fact, there are no adjustable regulators available commercially which have an output voltage Vout clamped to the substrate and that include inhibit circuitry integrated in the same semiconductor.
Until now, no circuit has been developed including inhibit circuitry referred to ground, such as TTL compatible circuitry, in an integrated circuit whose substrate is unrelated to ground and related to a higher potential, and may be supplied a lower voltage than that applied to the inhibit pin.
SUMMARY OF THE INVENTION
Embodiments of this invention provide an integrated circuit structure which has a voltage reference relative to ground and useful for external comparison with an inhibit voltage in order to activate or not an inhibit activation circuit portion referenced to the substrate. The remainder of the integrated circuit is referenced to the substrate. Circuit elements are used in the inhibit circuit portion which have an epitaxial layer of each well always at a potential higher than or equal to that of the substrate, and. which meet a condition of the inhibit voltage greater than the supply voltage. It thus becomes possible to ensure compatibility toward ground with any external interface, as well as ensuring that the substrate is biased with a voltage of the supply voltage less the minimum drop at its maximum, and that the condition of the inhibit voltage greater than the supply voltage are both met.
One embodiment of the invention provides for a ground-compatible inhibit circuit structure in a semiconductor substrate that is not referenced to the ground potential. The structure is integrated in the same substrate as an associated circuit to be inhibited, and the substrate is covered with an epitaxial layer accommodating the components of the inhibit circuit portion. The inhibit circuit includes a stable internal voltage reference and a circuit portion operative to compare the reference with an inhibit signal in order to block the associated circuit upon a predetermined threshold value being exceeded, even in a condition of the signal potential being higher than the supply potential to the circuit.
The features and advantages of a circuit structure according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 4736271 (1988-04-01), Mack et al.
patent: 5485109 (1996-01-01), Dobkin et al.
patent: 03058614 (1991
Dickey Thomas L
Iannucci Robert
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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