Ground bounce control using DLL to optimize output stage di/dt u

Details Ground bounce control using DLL to optimize output stage di/dt u Ground bounce control using DLL to optimize output stage di/dt u

1998-05-18

2000-11-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327161, 327387, 326 27, H03K 508

Patent

active

061540838

ABSTRACT:
A circuit for reducing the ground and power supply bounce of the output drivers in a group of I/O cells. A replica I/O cell is part of a delay locked loop which uses closed-loop feedback control to determine the magnitude of a bias current needed to cause the delay through the replica cell to be equal to a reference value. By forcing the delay through the replica cell to be equal to a desired reference value, the magnitude of bias current required to control the delay through each of the I/O cells in an I/O ring so that the delay approaches the reference value can be determined. As a result, by properly selecting the reference delay value, the magnitude of the bias current required to compensate for delay variations arising from multiple sources (e.g., PVT) can be determined. Since this reduces the rate of change of the current in the output drivers of the actual I/O cells, the induced voltage responsible for the ground and/or power supply bounce in those cells is reduced.

REFERENCES:
patent: 5336940 (1994-08-01), Sorrells et al.
patent: 5497105 (1996-03-01), Oh et al.
patent: 5719514 (1998-02-01), Sato
patent: 5768177 (1998-06-01), Sakuragi
C.S. Choy, M.H. Ku and C.F. Chan, "A Low Power-Noise Output Driver with an Adaptive Characteristic Applicalbe to a Wide Range of Loading Conditions", IEEE Journal of Solid State Circuits, vol. 32, No. 6, Jun. 1997, pp. 913-917.

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