Grooved DMOS process with varying gate dielectric thickness

Details Grooved DMOS process with varying gate dielectric thickness Grooved DMOS process with varying gate dielectric thickness

1987-12-29

1990-04-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 79, 437 41, 437913, 437 66, 148DIG168, 148DIG126, 148DIG50, 357 234, H01L 21283, H01L 2122

Patent

active

049140582

ABSTRACT:
Disclosed is a process for making a DMOS, including lining a groove with a dielectric material to form an inner groove having sidewalls extending through the bottom of the first groove, and lining the inner groove with a dielectric material to obtain increased thickness of the gate dielectric on the sidewalls of the inner groove.

REFERENCES:
patent: 3412297 (1968-11-01), Amlinger
patent: 3518509 (1970-06-01), Cullis
patent: 4520552 (1985-06-01), Arnould et al.
patent: 4546367 (1985-10-01), Schutten et al.
patent: 4553151 (1985-11-01), Schutten et al.
patent: 4622569 (1986-11-01), Lade et al.
Ueda et al., IEEE Trasactions on Electron Devices, vol. ED-32, No. 1, Jan. 1983, pp. 2-6.
Amar et al., IEEE Transactions on Electron Devices, vol. ED-27, No. 5, May 1980, pp. 907-914.
Sze, VLSI Technology, 1983, McGrawHill, pp. 145-149.

Affiliated with

Also associated with

Rating

Grooved DMOS process with varying gate dielectric thickness does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Grooved DMOS process with varying gate dielectric thickness, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Grooved DMOS process with varying gate dielectric thickness will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1357445