Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-03-09
2002-06-18
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S287000
Reexamination Certificate
active
06406357
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to techniques for grinding semiconductor substrates, a semiconductor device, and techniques for manufacturing the semiconductor device. More particularly, the present invention relates to techniques effectively applicable to finishing by grinding a surface of a semiconductor substrate, such as a wafer, to be used for manufacturing semiconductor devices including electronic parts, such as IC chips, applicable to portable information processing apparatus, such as portable telephone sets, mobile personal computers and IC cards, and electronic apparatus.
Semiconductor device manufacturing methods include a grinding process for grinding the back surface of a wafer, i.e., the surface opposite a surface of the wafer in which circuits are formed. This process generally follows a process for forming the circuits using photolithographic techniques and the like prior to subjecting the wafer to a dicing process for dividing the wafer into individual semiconductor devices.
The wafer which is to be subjected to the circuit forming process has a thickness of 500 &mgr;m or more to obtain adequate rigidity and strength necessary to withstand external forces that may be exerted thereon in the circuit forming process. Since the circuit functions of semiconductor devices, such as ICs and LSIs, are executed only in a surface layer of a thickness on the order of several micrometers of the wafer, an unnecessary portion of the wafer is removed by grinding to form a semiconductor device which is small, has lightweight construction and conforms to device requirements.
SUMMARY OF THE INVENTION
FIG. 10
shows a flow chart of a grinding method and a method for manufacturing a semiconductor device based on reference technology by way of example. The following analysis of existing technology is a part of the invention, particularly insofar as it relates to the identification or discovery of problems, causes of problems and solutions to problems flowing therefrom. The semiconductor device manufacturing method includes step S
1
for forming electronic circuits on a surface A (primary (first) surface in which circuits are to be formed) of a semiconductor substrate (wafer), step S
2
for roughly grinding a surface B (back (second) surface) of the wafer for a removable of oxide film and thickness adjustment, step S
3
for finish grinding the surface B of the wafer, step S
4
for chemical etching the surface B of the wafer with a chemical etchant, and step S
5
for dicing the wafer.
Principal conditions for the grinding processes to be carried out in steps S
2
and S
3
are shown in FIG.
10
. Visually recognizable grinding streaks are formed in the surface B of the semiconductor substrate finished by the finish grinding process specified by process conditions shown in FIG.
10
. The semiconductor substrate as finished by the finish grinding process in step S
3
specified by the conditions shown in FIG.
10
has a low deflective strength described below. Therefore, the surface B is finished by the chemical etching process in step S
4
before dicing the semiconductor substrate.
The chemical etching process in step S
4
drips or jets an etchant, such as a mixture of hydrofluoric acid and nitric acid, on the surface B of the rotating semiconductor substrate to dissolve the silicon of the semiconductor substrate. The chemical etching process is continued for a long period of time sufficient to etch and finish the semiconductor substrate to a desired thickness.
This grinding technique based on the reference technology requires a substantial chemical etching process for finishing the semiconductor substrate and hence the grinding technique takes more time. For example, the chemical etching process etches the surface B of the semiconductor substrate at an etch rate of about 5 &mgr;m/min. Suppose that an etching allowance of 150 &mgr;m is left on the semiconductor substrate in step S
3
. Then, the chemical etching process takes 30 min to finish one semiconductor substrate. When the etching allowance is reduced to reduce time necessary for the chemical etching process in step S
3
, the strength of the semiconductor substrate is reduced and the possibility of breakage of the semiconductor substrate increases.
Since the chemical etching process uses chemical liquids, such as hydrofluoric acid and nitric acid, liquid waste disposal is costly. It is necessary to provide the process equipment relating to the chemical etching process with chemical corrosion-resisting measures, which increases the manufacturing costs of the process equipment and the running costs.
When a semiconductor substrate is subjected to a chemical etching process, different portions of the semiconductor substrate are etched at different etch rates. Therefore it is difficult to control the thickness of the finished semiconductor substrate. For example, when the semiconductor substrate is finished in a thickness on the order of 30 &mgr;m, the differences in thickness between different portions of the semiconductor substrate poses a significant problem.
A semiconductor substrate finished to a thickness on the order of 30 &mgr;m by the finish grinding process has a low deflective strength. For example, even a minute flaw in a peripheral portion of the semiconductor substrate could develop into a large crack when it is deflected even slightly during transfer to the dicing process and, eventually, the semiconductor substrate may break.
Accordingly, it is a first object of the present invention to provide a technique capable of reducing the thickness of a semiconductor substrate by using only grinding processes.
A second object of the present invention is to provide a technique capable of achieving a high throughput when reducing the thickness of a semiconductor substrate.
A third object of the present invention is to provide a technique capable of preventing cracking of semiconductor substrates attributable to grinding processes.
A fourth object of the present invention is to provide a technique capable of: establishing a process that does not use chemical liquids, such as hydrofluoric acid and nitric acid thereby making liquid waste disposal unnecessary; reducing the cost by making chemical corrosion-resisting measures for the process equipment unnecessary; and reducing operating cost by making the use of chemical liquids unnecessary.
A fifth object of the present invention is to provide a technique capable of improving the accuracy of the thickness of a semiconductor substrate processed by a thickness reducing process.
According to the present invention, in a semiconductor substrate grinding process, a surface of a semiconductor substrate is ground by applying a rotating grinding wheel onto the surface of the semiconductor substrate which is also rotated. The surface of the substrate is finished by a process that brings a grinding wheel having fine abrasive grains that is rotating at a high rotating speed into contact with the semiconductor substrate. The semiconductor substrate is processed in a stable manner by reducing stress that is induced in the semiconductor substrate during the grinding process. For example, a grinding wheel formed by bonding abrasive grains of grain number #4000 (grain sizes in the range of 2 to 4 &mgr;m) is used for finishing the substrate and the grinding wheel is rotated at a high relative rotating speed with respect to the semiconductor substrate to prevent loading of the grinding wheel and to optimize the dressing cycle. The thickness of the semiconductor substrate is continuously measuring to determine the termination of the grinding process.
The present invention provides a semiconductor device manufactured by the above-mentioned method for manufacturing a semiconductor device.
The present invention can also include the use of a flash chemical etching process for finishing the semiconductor substrate before subjecting the semiconductor substrate to a dicing process. An etching allowance in terms of thickness for the chemical etching process can be minimized without
Kazui Shinichi
Morita Kenji
Odashima Hitoshi
Sasaki Hideaki
Shirase Kazuo
Hail III Joseph J.
Shakeri Hadi
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