Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2002-07-16
2004-09-28
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S786000, C438S612000
Reexamination Certificate
active
06798075
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a grid array (GA) packaged integrated circuit (IC), and more specifically, to a grid array packaged integrated circuit with reduced ground path impedance and improved yield for metal connection processes.
2. Description of the Prior Art
The desire for ever more compact electronic devices has pushed for size reductions in integrated circuits. When designing such circuits, both the internal impedances of the chip and the impedance of the bonding wires used for packaging must be taken into consideration to prevent signal distortion, signal lag and signal interaction. Reduced design size increase the difficulty of the manufacturing process, and therefore result in decreased yield. It is thus important to design and manufacture chips having low impedance without decreasing the yield.
Please refer to FIG.
1
.
FIG. 1
is a schematic diagram of a prior art grid array (GA) packaged integrated circuit (IC). The prior art IC comprises a substrate (not shown) and a chip
10
attached on the substrate. The chip
10
comprises a core circuit
11
and a plurality of I/O devices
12
along the periphery of the core circuit
11
. The layout method for the chip
10
divides the top metal layer in each I/O device
12
into four regions, from an inner most region to an outermost region. The four top metal layers surround the core circuit
11
as four metal rings by surrounding the I/O devices
12
along the periphery of the chip
10
. The four power rings (only one side is shown) are, from innermost region to outermost region, a core circuit ground ring (GND)
14
, a core circuit power ring (V
DD
)
16
, an I/O buffering circuit power ring (V
CC
)
18
, and an I/O buffering circuit ground ring (V
SS
)
22
. The four metal rings are sequentially arranged, from the center portion of the chip
10
to the outer periphery, as the I/O devices
12
, each having a striped shape to serve as power and ground sources to the internal circuit of the I/O device. Depending upon the application, the order of power and ground rings may be changed to more properly accommodate the layout of the I/O buffering circuit.
In other words, each I/O device comprises four different and separate I/O units: the core circuit ground I/O, core circuit power (V
DD
)I/O, I/O buffering circuit power (V
CC
) I/O and I/O buffering circuit ground (V
SS
) I/O. The four I/O units are arranged in sequence, aligned from the center portion of the chip to the outside, to form an I/O device having a striped shape.
On the surface of the chip
10
, outside the periphery of the plurality of the I/O devices
12
, are a plurality of bonding pads
26
(one side is shown only). The bonding pads
26
in the prior art grid array packaged integrated circuit
10
are arrayed in a two-tier staggered manner. An inner row of bonding pads, located closer to the center of the chip
10
, form the first row of bonding pads
28
, which are used as signal bonding pads. An outer row of bonding pads form the second row of bonding pads
32
, which are used as ground and power bonding pads, and sometimes signal bonding pads, according to the characteristics required by the circuit design.
The I/O devices
12
and the corresponding plurality of bonding pads
26
in the prior art integrated circuit have an one to one correspondence relationship. That is, each I/O device
12
corresponds to a bonding pad
26
, and the two are electrically connected to each other by metal traces (not shown) and vias (not shown). As shown in
FIGS. 1 and 2
, a ground ring
34
, a power ring
36
and signal fingers
38
are disposed on the substrate. Bonding pads of the first row
28
are electrically connected to the outermost signal fingers
38
through bonding wires
42
. The bonding pads of the second row
32
are electrically connected to the ground ring
34
or the power ring
36
through bonding wires
42
, respectively.
Power is supplied in the prior art integrated circuit chip
10
through the power ring
36
, bonding pads
26
, I/O devices
12
and finally to the core circuit
11
, in order. As noted earlier, the bonding pads
28
of the first row and the bonding pads
32
of the second row are arranged in a staggered manner (as shown in FIG.
1
). In order to satisfy high-density packaging requirements, the pad pitch between pads
26
must be reduced to accommodate more pads
26
and corresponding I/O devices
12
.
High-density designs shrink the pad pitch of the first row of bonding pads
28
and the second row of bonding pads
32
to increase bonding pads
26
. However, the chip size cannot be effectively reduced. Moreover, the total number of bonding pads
26
formed on the chip
10
is limited since the I/O devices
12
correspond to the bonding pads
26
in a one to one manner. As shown in
FIG. 3
, bonding pads
44
may also be arranged in a tri-tier manner in another prior art embodiment. However, although this arrangement will slightly increase the number of bonding pads, it does not reduce the chip size, nor sufficiently increases the total number of bonding pads to provide sufficient current branches and reduce the inductance. During high frequency operational ranges, inductance dominates the magnitude of the impedance (Z=R+j&ohgr;L). High impedance results in serious power/ground bounce and voltage degradation within the integrated circuit.
SUMMARY OF INVENTION
It is therefore an objective of the present invention to provide a grid array packaged chip that offers reduced chip sizes and reduced circuit impedance to solve the above-mentioned problems.
Briefly, the present invention discloses a grid array packaged integrated circuit that includes a substrate and a chip with a core circuit. The chip is disposed on the substrate. The chip includes I/O devices, bonding pads arranged on the chip in a multi-tier manner surrounding the I/O devices, metal traces and vias on metal layers of the chip for electrically connecting each I/O device and each bonding pad, rings and fingers surrounding the chip on the substrate, and bonding wires for electrically connecting each bonding pad to a corresponding finger or to a corresponding ring. Bonding pads electricaly connected to different voltage levels can share the same I/O device.
It is an advantage that the present invention provides a greater number of power and ground bonding pads, and thus enables sufficient current branches to reduce the total impedance of the circuit. Additionally, the disposition of bonding wires is such that their total lengths are kept minimal, thus further reducing circuit impedance.
These and other objectives of the present invention will become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments accompanied with the drawings.
REFERENCES:
patent: 5796171 (1998-08-01), Koc et al.
patent: 5814892 (1998-09-01), Steidl et al.
patent: 6638793 (2003-10-01), Chen
patent: 2004/0004296 (2004-01-01), Cheng et al.
Chang Wen-Yuan
Liaw Yuang-Tsang
Tsai Hung-Yin
Chambliss Alonzo
Hsu Winston
VIA Technologies Inc.
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