Gray voltage generation circuit for driving a liquid crystal...

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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Details

C345S092000, C345S096000

Reexamination Certificate

active

06670935

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a liquid crystal display and, more particularly, to a gray voltage generation circuit for driving a liquid crystal display and such a liquid crystal display.
BACKGROUND OF THE INVENTION
Generally, a liquid crystal is an organic compound having a neutral property between liquid and crystal, and changes in its color or transparency by voltage or temperature. A liquid crystal display (LCD), which expresses information using the liquid crystal, occupies a smaller volume and has a lower power consumption than a conventional display device. Therefore, lots of attentions are paid to the LCD as a novel display device.
FIG. 1
schematically illustrates a configuration of a conventional liquid crystal display. A liquid crystal display
10
includes a liquid crystal panel
1
, a gate driving circuit
2
coupled to the liquid crystal panel
1
, a source driving circuit
3
, a timing control circuit
4
, and a gray voltage generation circuit (or gamma reference voltage generation circuit)
5
.
The liquid crystal panel
1
is made of a plurality of gate lines G
0
through Gn and a plurality of data lines D
1
through Dm that are vertically interconnected with the gate lines, respectively. The gate driving circuit
2
is connected to each of the gate lines G
0
through Gn, and the source driving circuit
3
is connected to each of the data lines D
1
through Dm. One pixel is composed in each interconnection of the gate lines and the data lines. Each pixel is made of one thin film transistor (TFT), one storing capacitor Cst, and one liquid crystal capacitor Cp. Each of pixels composing the liquid crystal panel
1
further includes three sub-pixels corresponding to red (R), green (G), and blue (B). A pixel displayed via the liquid crystal panel
1
is obtained by combination of R, G, and B color filters. The liquid crystal display
10
can display not only color pictures but also pure red, green, blue, and gray scales by combining those pixels.
The timing control circuit
4
issues control signals (e.g., gate clock and gate on signals) required in the gate driving circuit
2
and the source driving circuit
3
in response to color signals R, G, and B, horizontal and vertical synch signals HSync and Vsync, and a clock signal CLK. The gray voltage generation circuit
5
is connected to the source driving circuit
3
, generating a gray voltage Vgray or a gamma reference voltage that is a reference to generate a liquid crystal driving voltage Vdrive. One example of the gray voltage generation circuit
5
is disclosed in U.S. Pat. No. 6,067,063 entitled “LIQUID CRYSTAL DISPLAY HAVING A WIDE VIEW ANGLE AND METHOD FOR DRIVING THE SAME”, issued to Kim et al., issued on May 23, 2000. A gray voltage generation circuit
5
disclosed therein includes a plurality of resisters R
1
through Rn+1 that are directly coupled between a power supply voltage (Vcc) and a ground (GND). Each of the resisters R
1
through Rn+1 distributes the power supply voltage (Vcc) with a predetermined ratio, generating n-bit gray voltages VG
1
through VGn.
Now, operations of the liquid crystal display
10
having such a configuration will be described in detail. If the gate driving circuit
2
sequentially scans pixels of the panel row by row, the source driving circuit
3
generates a liquid crystal driving voltage Vdrive based upon the color signals R, G, and B inputted through the timing control circuit
4
, in response to the reference voltage Vgray outputted from the gray voltage generation circuit
5
. And then, the source drive
3
applies the generated voltage Vdrive to the panel
1
each time of scanning.
In such an operation, the TFT acts as a switch. For example, when the TFT is turned on, the liquid crystal capacitor Cp is charged by the liquid crystal driving voltage Vdrive generated from the source driving circuit
3
. When the TFT is turned off, the capacitor Cp prevents the charged voltage from leaking. This shows that the liquid crystal driving voltage Vdrive applied from the source driving circuit
3
has a great influence upon driving each TFT composing the panel
1
.
As the liquid crystal display tends to implement high speed response, it is required to enhance a response speed of such a liquid crystal display Cp in order to speed up the device. This is because if the voltage Vdrive applied from the source driving circuit
3
has a high value, the capacitor Cp would quickly be charged to enhance a total driving speed of a liquid crystal display.
There are many methods of boosting a liquid crystal driving voltage Vdrive applied from the source driving circuit
3
in order to enhance a driving speed of the liquid crystal display. For example, it requires a design change of the gate driving circuit
2
or the source driving circuit to generate a liquid crystal driving voltage Vdrive of high level, or a design change of the timing control circuit
4
for issuing a control signal to the driving circuits
2
and
3
. Unfortunately, changing designs of such high-priced circuits causes higher costs in a production unit. Furthermore, the increased liquid crystal driving voltage Vdrive also increases power consumption of the liquid crystal display in proportion to the voltage Vdrive rise.
Accordingly, the object of the present invention is to overcome the foregoing drawbacks, and to provide a gray voltage generation circuit that can enhance a driving speed of a liquid crystal display with low cost and power consumption.
SUMMARY OF THE INVENTION
To attain this object, there is provided a liquid crystal display that includes a liquid crystal panel having a plurality of pixels, a gray voltage generation circuit for generating a plurality of gray voltages corresponding to data to be displayed in the liquid crystal panel, a timing control circuit for issuing a gate clock signal and a plurality of control signals, a gate driving circuit for sequentially scanning the pixels row by row in response to the gate clock signal, and a source driving circuit for generating a liquid crystal driving voltage in response to the data and applying the generated liquid crystal driving voltage to the panel each time of scanning. In response to the gray voltage, the source driving circuit generates a liquid crystal driving voltage that has different values in high and low level intervals.


REFERENCES:
patent: 6118421 (2000-09-01), Kawaguchi et al.
patent: 6310592 (2001-10-01), Moon et al.
patent: 6556180 (2003-04-01), Furuhashi et al.
patent: 6567062 (2003-05-01), Kudo et al.

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