Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2001-06-28
2004-09-21
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S520000, C345S506000
Reexamination Certificate
active
06795076
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to a flexible system architecture for generating video signals in a graphics environment.
2. Description of the Related Art
A computer system may be used to drive one or more display devices (such as monitors or projectors). The computer system may provide analog or digital video signals to drive the display devices. The computer system may include a graphics system for the rendering and display of 2D graphics and/or 3D graphics. The graphics system may supply the video signals which drive the display devices. In addition, the computer system may include a system unit, and input devices such as a keyboard, mouse, etc.
In general, prior art graphics systems do not have a scalable video architecture, i.e. they are not able to flexibly allocate hardware resources in proportion to the number of video signals to be generated and the respective pixel bandwidths of the video signals. Thus, graphics consumers are often forced to use a more powerful, and thus, more expensive graphics system than would be optimal for a given graphics scenario. Thus, there exists a need for a graphics system which could flexibly allocate hardware resources to video signals in proportion to their respective pixel bandwidths.
Furthermore, prior art graphics systems typically do not provide a mechanism enabling multiple hardware devices (e.g. graphics boards) to collaborate in generating one or more video signals. Thus, graphics consumers may be forced into the inefficient mode of using one hardware device (e.g. one graphics board) per video signal. In this case, some or all of the graphics boards may operate at significantly less than maximum capacity. Therefore, there exists a need for a graphics system and methodology which could enable multiple hardware devices to collaborate in the generation of one or more video signals.
For many reasons, users of a graphics system often desire to capture into system memory (or some other memory) one or more frames of video generated by the graphics system. Thus, more particularly, there exists a need for a graphics system configured to collaboratively generate one or more video signals and simultaneously transfer selected frames (or portions of frames) to a selected memory destination.
SUMMARY OF THE INVENTION
In one set of embodiments, a graphics system may be configured to (a) generate one or more video signals in response to received graphics data and (b) transfer to a desired target memory selected frames (or portions of frames) of a selected one of the video signals. The graphics system may comprise a control unit and a series of calculation units. The control unit is configured for coupling to a host computer though an interconnecting bus. The series of calculation units may be configured to generate the one or more video streams in response to sample data accessed from a sample buffer.
Each of the calculation units in the series may be programmably assigned to generate image pixels for a portion (e.g. a rectangular region) of one of the video streams. Each calculation unit contributes its locally generated image pixels to its assigned video stream. Thus, a video stream gradually matures from a null stream of dummy pixels to a completed video stream as it passes through successive calculation units.
A segmented communication bus comprising multiple bus segments couples the control unit and the calculation units in a closed chain configuration. Data may flow around the chain in one direction. Thus, the data interface between successive elements in the chain (i.e. the control unit and the calculation units) may have a simple structure.
The control unit may receive a get frame request from the host computer through the interconnecting bus. The get frame request may specify (a) one of the calculation units which is to source a transfer of video pixels, (b) a target block in a target memory which is serve as the destination of the pixel transfer, (c) one of the video streams from which the video pixels are to be taken, and (d) a subset of the specified video stream from which video pixels are to be taken. The control unit transmits a frame readback request to the selected calculation unit, i.e. the calculation unit selected in (a), through the segmented communication bus. The frame readback request may include an indication of selected video stream and the selected video pixel subset. The selected subset of the selected video stream may be a rectangular window in a frame of the selected video stream. In one embodiment, the selected subset is a rectangular window in the “next frame”, i.e. the frame immediately following the get frame request. It should be noted that according to standard mathematical usage, a subset Y of a set X may equal X or something less than X. Thus, the selected subset may comprise the whole of the next frame.
In response to receiving the frame readback request, the selected calculation unit may transfer the selected subset of the selected video stream to the control unit through the segmented communication bus. The control unit forwards the selected subset of video pixels to the target block in the target memory. The target memory may be the system memory of the computer. In some embodiments, the target memory may also be a memory resident within the graphics system. The control unit may include a DMA engine to facilitate the video pixel transfer within host CPU intervention.
In some embodiments, the segmented communication bus also supports read and write transactions from/to memory locations (e.g. control registers, data tables, etc.) in the calculation units. Thus, a host application executing on the host computer may control the state of any or all of the calculation units by writing to calculation units through the control unit and segmented communication bus. Also, the host application may read memory locations in any of the calculation unit through the segmented communication bus. This read mechanism may be used to gather debug data or collect operational statistics from the calculation units.
REFERENCES:
patent: 6100899 (2000-08-01), Ameline et al.
patent: 2002/0000988 (2002-01-01), Nelson et al.
patent: 2003/0122815 (2003-07-01), Deering
“OpenGL Reference Manual”, 1992, pp. 252-256.
Thermal Performer Webpage www.dorbie.com/thermal.html, 1998, 5 pages.
SGIX Webpage http://oss.sgi.com/projects/ogl-sample/registry/SGIX/async-pixel.txt, 1998, 4 pages.
Deering Michael F.
Naegle Nathaniel David
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
Tung Kee M.
LandOfFree
Graphics system with real-time convolved pixel readback does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Graphics system with real-time convolved pixel readback, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Graphics system with real-time convolved pixel readback will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3224102