Graphics system with programmable tile size and multiplexed pixe

Details Graphics system with programmable tile size and multiplexed pixe Graphics system with programmable tile size and multiplexed pixe

1987-08-18

1990-10-23

Harkcom, Gary V.

Boots, shoes, and leggings

340723, 364900, G06F 1520

Patent

active

049657518

ABSTRACT:
A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in eac group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. A pixel data/partial address muliplexing method based on programmable tile size reduces the number of interconnections between a pixel interpolator and the frame buffer without significantly increasing the number of bus cycles needed to transfer the information. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput.

REFERENCES:
patent: 4109310 (1978-08-01), England et al.
patent: 4570181 (1986-02-01), Yamamura
patent: 4694288 (1987-09-01), Harada
patent: 4755810 (1988-07-01), Knierim
patent: 4777485 (1988-10-01), Costello
patent: 4800380 (1989-01-01), Lowenthal et al.

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