Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Reexamination Certificate
2001-10-04
2003-02-11
Nguyen, Phu K. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
Reexamination Certificate
active
06518965
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
The following applications are related to the present application, and are hereby incorporated by reference as though fully and completely set forth herein:
Ser. No. 08/340,667 titled “Integrated Video and Memory Controller With Data Processing and Graphical Processing Capabilities” and filed Nov. 16, 1994;
Ser. No. 08/463,106 titled “Memory Controller Including Embedded Data Compression and Decompression Engines” and filed Jun. 5, 1995;
Ser. No. 08/916,464 titled “Memory Controller Including Embedded Data Compression and Decompression Engines” and filed Aug. 8, 1997;
Ser. No. 09/241,139 titled “Memory Controller Including Embedded Data Compression and Decompression Engines” and filed Feb. 1, 1999;
Ser. No. 08/565,103 titled “Memory and Graphics Controller Which Performs Pointer-Based Display List Video Refresh Operations” and filed Nov. 30, 1995, which has issued as U.S. Pat. No. 5,838,334;
Ser. No. 08/770,017 titled “System and Method for Simultaneously Displaying a Plurality of Video Data Objects Having Different Bit Per Pixel Formats” and filed Dec. 19, 1996;
Ser. No. 08/604,670 titled “Graphics System Including a Virtual Frame Buffer Which Stores Video/Pixel Data in a Plurality of Memory Areas” and filed Feb. 21, 1996;
Ser. No. 09/056,021 titled “Video/Graphics Controller Which Performs Pointer-Based Display List Video Refresh Operations” filed on Apr. 6, 1998;
Ser. No. 09/239,659 titled “Bandwidth Reducing Memory Controller Including Scalable Embedded Parallel Data Compression and Decompression Engines” whose inventors are Thomas A. Dye, Manuel J. Alvarez II, and Peter Geiger, and filed on Jan. 29, 1999.
FIELD OF THE INVENTION
The present invention relates to computer system graphics architectures, and more particularly to a graphics controller which performs pointer-based display list video operations to build and manipulate two and three dimensional objects and transfer the objects video data from a memory to a display device.
DESCRIPTION OF THE RELATED ART
Since their introduction in 1981, the architecture of personal computer systems has remained substantially unchanged. The current state of the art in computer system architectures includes a central processing unit (CPU) which couples to a memory controller interface that in turn couples to system memory. The computer system also includes a separate graphical interface for coupling to the video display. In addition, the computer system includes input/output (I/O) control logic for various I/O devices, including a keyboard, mouse, floppy drive, hard drive, etc.
In general, the operation of a modern computer architecture is as follows. Programs and data are read from a respective I/O device such as a floppy disk or hard drive by the operating system, and the programs and data are temporarily stored in system memory. Once a user program has been transferred into the system memory, the CPU begins execution of the program by reading code and data from the system memory through the memory controller. The application code and data are presumed to produce a specified result when manipulated by the system CPU. The code and data are processed by the CPU and data is provided to one or more of the various output devices. The computer system may include several output devices, including a video display, audio (speakers), printer, etc. In most systems, the video display is the primary output device.
Graphical output data generated by the CPU is written to a graphical interface device for presentation on the display monitor. The graphical interface device may simply be a video graphics array (VGA) card, or the system may include a dedicated video processor or video acceleration card including separate video RAM (VRAM). In a computer system including a separate, dedicated video processor, the video processor includes graphics capabilities to reduce the workload of the main CPU. Modern prior art personal computer systems typically include a local bus video system based on either the peripheral component interconnect (PCI) bus or the VESA (Video Electronics Standards Association) VL bus, or perhaps a proprietary local bus standard. The video subsystem is generally positioned on a local bus near the CPU to provide increased performance.
Therefore, in summary, program code and data are first read from the hard disk to the system memory. The program code and data are then read by the CPU from system memory, the data is processed by the CPU, and graphical data is written to the video RAM in the graphical interface device for presentation on the display monitor. The CPU typically reads data from system memory across the system bus and then writes the processed data or graphical data back across the system bus to the I/O bus or local bus where the graphical interface device is situated. The graphical interface device in turn generates the appropriate video signals to drive the display monitor. It is noted that this operation requires data to make two passes across the system bus and/or the I/O subsystem bus. In addition, the program that manipulates the data must also be transferred across the system bus from the main memory. Further, two separate memory subsystems are required, the system memory and the dedicated video memory, and video data is constantly being transferred from the system memory to the video memory frame buffer.
One recent trend in computer system architecture and design is referred to as a “shared” or “unified” memory, also referred to as a unified memory architecture (UMA). In this architecture, the main or system memory is used for operating system and applications software as well as for the video frame buffer. However, one problem with the “unified” or “shared” memory approach is the perceived need for additional bandwidth to perform video functions such as bit block transfers and video refresh, rasterization and display of three dimensional objects, as well as CPU manipulation of programs and data within the same memory subsystem.
Current 3D display system use a method called the “immediate” mode to render 3D objects. This mode draws a single triangle at a time checking a Z-buffer and reading a texture map or other source data to cover each single triangle. This prior art requires increased memory bandwidth due to triangles that are completely drawn and new triangles that overlap or hide previously drawn triangles. UMA architectures that use immediate mode 3D will be slower and lower performance due to these limitations.
Computer systems are being called upon to perform larger and more complex tasks that: require increased computing power. In addition, modern software applications require computer systems with increased graphics capabilities. Modem software applications typically include graphical user interfaces (GUIs) which place increased burdens on the graphics capabilities of the computer system. Further, the increased prevalence of multimedia applications, such as digital video and 3D graphics, also demands computer systems with more powerful graphics capabilities. Therefore, a new computer system and method is desired which provides increased system performance while reducing system cost, in particular, increased video and 2D/3D graphics performance than that possible using prior art.
SUMMARY OF THE INVENTION
The present invention comprises a video, 2D and 3D graphics controller, also referred to as the Integrated Memory Controller (IMC), which includes a novel spanning based system and method for rendering and display of 2D and 3D graphical data on a display device or video monitor, preferably using the main system memory in a unified or shared manner. The novel object based and spanning based display refresh list system for display of 2D and 3D graphical data can also be used within a graphics adapter with it's own local memory system. The IMC performs pointer-based display list video operations for rendering of 2D and 3D video data. The graphics controller of the present invention minimizes data movement for 2D/3D and video data manipulation for video display
Alvarez, II Manuel J.
Dye Thomas A.
Geiger Peter D.
Hood Jeffrey C.
Interactive Silicon, Inc.
Nguyen Phu K.
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