Graphics subsystem with smart direct-memory-access operation

Details Graphics subsystem with smart direct-memory-access operation Graphics subsystem with smart direct-memory-access operation

1995-03-24

1998-07-07

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345519, 345505, 345526, G06T 0120

Patent

active

057776296

ABSTRACT:
A graphics subsystem using a smart DMA controller to perform DMA data loading with some modified addressing. The DMA controller can operate in an incremental mode, in a hold mode (where each chunk of data is written into the same address), or in an indexed mode. The buffer registers are assigned to groups, and, in the indexed mode, a header in the DMA buffer precedes any data for a group. The header identifies the recipient group and each register (in the group) to be updated has its corresponding bit set. Thus a high-efficiency DMA operation is obtained even in cases when increment mode cannot be used directly, e.g. when not all registers in a group need to be written, and/or the registers which need to be written are not contiguous.

REFERENCES:
patent: 4967375 (1990-10-01), Pelham et al.
patent: 5392391 (1995-02-01), Caulk, Jr. et al.
Miner et al., "A low cost imaging workstation using the Commodore Amiga and NEC's Image Pipelined Processors" Electronic Imaging '88, pp. 422-427.
Taniguchi et al., "A Distributed-Memory Multi-Thread Multiprocessor Architecture for Computer Vision and Image Processing: Optimized Version of AMP" Proc. Twenty-Sixth Hawaii International Conf. on System Science, pp. 151-160 (1993).

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