Graphics subsystem with coarse subpixel correction

Details Graphics subsystem with coarse subpixel correction Graphics subsystem with coarse subpixel correction

1995-03-24

1997-01-14

Jankus, Almis R.

395501, 395506, G06T 1500

Patent

active

055948545

ABSTRACT:
A graphics processing system in which sub-pixel correction is implemented in a new and more economical way. A half-pixel offset is originally imposed on both the X and Y axes, so the sub-pixel correction value may be positive or negative. A relatively coarse resolution is used for subpixel correction, so that the DDAs (and other functional blocks) do not have to perform a full multiply: instead they merely perform simple add operations (addition of partial products) to derive the necessary offset from the delta-X values, using a proportionality constant provided by the rasterizer. The DDAs preferably include a "guard band" in their calculations, so that values which exceed the maximum (e.g. 255, for 8 bits of subpixel resolution) do not wrap to zero; instead the output is held at the maximum until the computed value comes down below the maximum.

REFERENCES:
patent: 5440682 (1995-08-01), Deering
Dunnett et al., "The Image Chip for High Performance 3D Rendering," IEEE Computer Graphics & Applications, pp. 41-52 (1992).
Gharachorloo et al., "Subnanosecond Pixel Rendering with Million Transistor Chips," Computer Graphics, vol. 4, pp. 41-49 (1988).
Akeley et al., "High-Performance Polygon Rendering," Computer Graphics, vol. 22, pp. 239-46 (1988).
Molnar et al., "Pixelflow: High-Speed Rendering Using Image Composition," Computer Graphics, vol. 26, pp. 231-240 (1992).
Akeley, "RealityEngine Graphics," Computer Graphics Proc., 109-16 (1993).
Harrell, "Graphics Rendering Architecture for a High Performance Desktop Workstation," Computer Graphics Proc., pp. 93-100 (1993).
Kirk et al., "The Rendering Architecture of the DN10000VS," Computer Graphics, vol. 24, pp. 299-307 (1990).

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