Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1998-06-23
2001-02-06
Chauhan, Ulka J. (Department: 2776)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S520000, C345S519000
Reexamination Certificate
active
06184907
ABSTRACT:
BACKGROUND OF THE INVENTION
In modern data processing systems, for example personal computers (PCs) and workstations, graphics subsystems perform the task of graphic data processing. Graphic data is exchanged between a host processor (CPU) and a video display device such as a cathode ray tube (CRT) device, a liquid crystal display (LCD) device, or the like. Display devices commonly support one or more pixel resolutions, for example, VGA mode (640×480 pixels), Super VGA (SVGA) mode (800×600), and Extended Graphics Array (XGA) mode (1024×768). With the advent of high-powered processors, for example Pentium™ processors and increasingly-sophisticated operating systems, for example Windows™ operating systems, capable of absorbing hardware differences, graphics subsystems have been integrated into a single chip so as to reduce their production costs and power consumption. These integrated graphics chips are commonly referred to as “graphics accelerators”.
Graphics accelerators commonly employ multi-port Video RAMS (VRAMs), which include an additional serial port for faster throughput and are therefore suitable for use in high-end applications. To further improve performance, contemporary systems include integrated circuits which improve system speed and conserve space by integrating larger parts of the graphics subsystem, either the logic and standard dynamic RAM (DRAM) separately or the entire subsystem, into the DRAM. These integrated graphics systems are developed for portable applications such as notebook size computers. These forms of RAM are referred to as “multiported” because they include two ports which provide different functions: the random port interfaces with the processor or controller; the serial port provides fast data to the video display devices by means of a wide parallel transfer internal to the RAM. A serial register required for the serial port increases the cost of the VRAM, however, and the larger, more expensive package size resulting from the dual ports, and therefore increased pin count, consumes more space on the PC board. The testing procedure is also more complex for the multi-port VRAM which increases manufacturing costs.
The data rate of the single-port DRAM has increased significantly with the introduction of the Extended Data Out mode, (EDO) or Hyperpage mode, and with the introduction of synchronous DRAMs with very wide interfaces. This has led to the increased use of fast, wide, single port DRAMs in graphics subsystems, coupled with the use of standard graphics accelerators which provide the multi-port interface to the processor and the RAMDAC (Random Access Memory Digital-to-Analog Computer). Many single-port DRAM variants are also being developed such as the synchronous graphics DRAMs and the Multi-bank DRAM.
To effectively communicate with single port DRAMs for computer graphics, graphics accelerators usually include a first-in first-out (FIFO) buffer. In a graphics accelerator with a FIFO buffer, a certain amount of video data, for example the capacity of the FIFO, is read from a frame buffer into the FIFO buffer, where it is passed on to a video display device. The frequency of access of the graphics accelerator to the FIFO buffer is therefore determined by the FIFO capacity A higher FIFO access frequency decreases the frame buffer access time of the CPU. This, in turn, causes considerable system performance degradation, particularly, in the case where a single-port RAM is employed as a frame buffer.
With the advent of high-definition television (HDTV) and large screen television (TV) and the rapid advancement of multimedia PCs, there is a heightened demand for graphics accelerators suitable for use with television video signals. To meet this demand, graphics accelerators now include video encoders which convert computer video signals into video signals suitable for television. A graphics accelerator with a. video encoder is capable of displaying computer-processed images on a television screen, by transferring video data stored in frame buffer to a television via a FIFO buffer. However, when computer video data in the form of widely used progressive scan or non-interlaced formats is converted by a video encoder into interlace-scan television video data for display on a television screen, flickers visible to the human eye occur, which adversely affects image quality.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a graphics system for use with a digital computer system capable of displaying high-quality images on a display screen by performing real-time interpolation of video data. Particularly, the present invention is applicable to graphics systems utilizing single-port memories as frame buffers.
According to an aspect of the present invention, a graphics subsystem utilizes a single port DRAM as a frame buffer. The frame buffer includes an r-bit wide data access port (where, r is a positive integer) that stores R (red), G (green), and B (blue) video data generated by an application program executed on a host processor. The graphics subsystem further includes a first-in first-out (FIFO) buffer for storing the video data from the frame buffer, and a scan interpolator for performing vertical and horizontal interpolation of data read from the FIFO buffer with respect to a predetermined number of adjacent scan lines, for example three lines on a video frame. A display controller generates a first control signal D_EN synchronized with a horizontal synchronizing signal and designating display enable periods. The FIFO buffer generates a second control signal M RQ when there exists at least one vacant storage location therein. A memory controller controls read and write operations of the frame buffer and FIFO buffer in response to the second control signal M_RQ from the FIFO buffer.
In a preferred embodiment, each scan line includes p scan blocks, where p is a positive integer. Each scan block is formed of q pixel data packets, and each pixel data packet is an r-bit wide video data corresponding to one or more pixels, where q and r are positive integers. The scan interpolator performs the interpolation of the video data associated with three adjacent scan lines. The memory controller controls the frame buffer in response to the second control signal M_RQ in such a manner that a first data of 3×q×r bits and a second data of 3×q×r bits, which correspond to first scan blocks of the three adjacent scan lines and second scan blocks of the three adjacent scan lines, respectively, are read out from the frame buffer sequentially and successively while the first control signal D_EN remains inactive. Also, the memory controller controls the frame buffer in response to the second control signal M RQ in such a manner that a third data of 3×q×r bits and a fourth data of 3×q×r bits, which correspond to odd-numbered scan blocks of the three adjacent scan lines and even-numbered scan blocks of the three adjacent scan lines, respectively, are read out from the frame buffer alternately and at a predetermined time interval while the first control signal D_EN remains active. The frame buffer preferably operates in a burst read out mode where q×r bits of data relating to each scan line are successively read out from the frame buffer.
The FIFO buffer preferably includes first and second storage regions which have identical storage capacity. The FIFO buffer stores the data read out of the frame buffer into the first and second storage regions sequentially in response to a third control signal W_EN from the memory controller while the first control signal D_EN remains inactive. While the first control signal D_EN remains active, the FIFO buffer provides 3×r bits of data, which are stored in one of the first and second storage regions and correspond to a column of the adjacent scan lines, to the scan interpolator in response to a fourth control signal R_EN from the display controller, and stores the data read out of the frame buffer in the other of the firs
Chauhan Ulka J.
Samsung Electronics Co,. Ltd
Samuels , Gauthier & Stevens, LLP
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