Graphics processor writing to shadow register at predetermined a

Details Graphics processor writing to shadow register at predetermined a Graphics processor writing to shadow register at predetermined a

1995-06-07

1997-12-09

Moore, David K.

395416, 395410, 395427, 395428, G06F 926, G06F 934, G06F 1200, G06F 1202

Patent

active

056969236

ABSTRACT:
A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.

REFERENCES:
patent: 5129059 (1992-07-01), Hannah et al.
patent: 5428754 (1995-06-01), Baldwin et al.
patent: 5446904 (1995-08-01), Belt et al.

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