Graphics processor with staggered memory timing

Details Graphics processor with staggered memory timing Graphics processor with staggered memory timing

1991-01-23

1992-07-07

Harkcom, Gary V.

Static information storage and retrieval

Magnetic bubbles

Guide structure

36518912, G06F 1500

Patent

active

051290596

ABSTRACT:
A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each to of the RAMs.

REFERENCES:
patent: 4673930 (1987-06-01), Bujalski et al.
patent: 4674064 (1987-06-01), Vaughn
patent: 4796232 (1989-01-01), House
patent: 4800530 (1989-01-01), Itoh et al.
patent: 4814969 (1989-03-01), Kiyooka
patent: 4903217 (1990-02-01), Gupta et al.
patent: 4912658 (1990-03-01), Sfarti et al.
patent: 4991110 (1991-02-01), Hannah

Affiliated with

Also associated with

Rating

Graphics processor with staggered memory timing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Graphics processor with staggered memory timing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Graphics processor with staggered memory timing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1836470